Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11432
-gerrit
commit e8c43021551387782c1830f933c1d491723eed81 Author: Wenkai Du wenkai.du@intel.com Date: Mon Aug 24 10:31:30 2015 -0700
intel/kunimitsu: fix SCI handling
Ported below patch from glados to kunimitsu:
glados: Abstract board GPIO configuration in gpio.h Original-change-Id: I3f1754012158dd5c7d5bbd6e07e40850f21af56d Originally-signed-off-by: Duncan Laurie dlaurie@chromium.org Originally-reviewed-on: https://chromium-review.googlesource.com/293942
BUG=chrome-os-partner:40828 BRANCH=none TEST=Verify that acpi interrupts are incrementing on kunimitsu.
Change-Id: Ifeddb34289b6e62c936cf6c542906d6e7ef96ddd Signed-off-by: Patrick Georgi patrick@georgi-clan.de Original-Commit-Id: 8ff0dd2dcdf6485f0171fb967f7de3015cf4e4ad Original-Change-Id: I1f270a03a241d2285639f79854d04059d2c2c99f Original-Signed-off-by: Wenkai Du wenkai.du@intel.com Original-Reviewed-on: https://chromium-review.googlesource.com/295048 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org Original-Reviewed-by: Robbie Zhang robbie.zhang@intel.com Original-Tested-by: Robbie Zhang robbie.zhang@intel.com --- src/mainboard/intel/kunimitsu/acpi/chromeos.asl | 10 +++++++--- src/mainboard/intel/kunimitsu/acpi/ec.asl | 3 ++- src/mainboard/intel/kunimitsu/acpi/mainboard.asl | 6 +++++- src/mainboard/intel/kunimitsu/chromeos.c | 3 +++ src/mainboard/intel/kunimitsu/ec.h | 5 ----- src/mainboard/intel/kunimitsu/gpio.h | 15 +++++++++++++++ src/mainboard/intel/kunimitsu/smihandler.c | 1 + 7 files changed, 33 insertions(+), 10 deletions(-)
diff --git a/src/mainboard/intel/kunimitsu/acpi/chromeos.asl b/src/mainboard/intel/kunimitsu/acpi/chromeos.asl index c6665f9..d3ab569 100644 --- a/src/mainboard/intel/kunimitsu/acpi/chromeos.asl +++ b/src/mainboard/intel/kunimitsu/acpi/chromeos.asl @@ -18,7 +18,11 @@ * Foundation, Inc. */
-Name (OIPG, Package() { - Package () { 0x0001, 0, 0xFFFFFFFF, "INT3437:00" }, // no recovery button - Package () { 0x0003, 1, 16, "INT3437:00" }, // firmware write protect +#include "../gpio.h" + +Name (OIPG, Package () { + /* No physical recovery GPIO. */ + Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" }, + /* Firmware write protect GPIO. */ + Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" }, }) diff --git a/src/mainboard/intel/kunimitsu/acpi/ec.asl b/src/mainboard/intel/kunimitsu/acpi/ec.asl index 9ef2553..63c45de 100644 --- a/src/mainboard/intel/kunimitsu/acpi/ec.asl +++ b/src/mainboard/intel/kunimitsu/acpi/ec.asl @@ -18,7 +18,8 @@ */
/* mainboard configuration */ -#include <mainboard/intel/kunimitsu/ec.h> +#include "../ec.h" +#include "../gpio.h"
/* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl index aa752f9..4492a19 100644 --- a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl +++ b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl @@ -18,6 +18,8 @@ * Foundation, Inc. */
+#include "../gpio.h" + #define BOARD_TRACKPAD_IRQ 0x33 #define BOARD_TOUCHSCREEN_IRQ 0x1f
@@ -36,11 +38,13 @@ Scope (_SB) { Return (_SB.PCI0.LPCB.EC0.LIDS) } + + Name (_PRW, Package () { GPE_EC_WAKE, 5 }) }
Device (PWRB) { - Name(_HID, EisaId("PNP0C0C")) + Name (_HID, EisaId("PNP0C0C")) } } /* diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 6767705..66d1a42 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -26,6 +26,9 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h>
+#include "gpio.h" +#include "ec.h" + #if ENV_RAMSTAGE #include <boot/coreboot_tables.h>
diff --git a/src/mainboard/intel/kunimitsu/ec.h b/src/mainboard/intel/kunimitsu/ec.h index 9c8a9d1..6408815 100644 --- a/src/mainboard/intel/kunimitsu/ec.h +++ b/src/mainboard/intel/kunimitsu/ec.h @@ -22,11 +22,6 @@ #define MAINBOARD_EC_H
#include <ec/google/chromeec/ec_commands.h> -#include <soc/gpio.h> - -/* GPP_E16 is EC_SCI_L */ -#define EC_SCI_GPI 16 /* TODO: Update this */ -#define EC_SMI_GPI GPP_E15
#define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h old mode 100644 new mode 100755 index f1166c8..0ab36f1 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -21,8 +21,21 @@ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H
+#include <soc/gpe.h> #include <soc/gpio.h>
+/* EC in RW */ +#define GPIO_EC_IN_RW GPP_C6 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_C23 +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK +/* GPP_E16 is EC_SCI_L. GPP_E group is routed to dword 2 in the GPE0 block. */ +#define EC_SCI_GPI GPE0_DW2_16 +#define EC_SMI_GPI GPP_E15 + +#ifndef __ACPI__ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), @@ -198,3 +211,5 @@ static const struct pad_config early_gpio_table[] = { };
#endif + +#endif diff --git a/src/mainboard/intel/kunimitsu/smihandler.c b/src/mainboard/intel/kunimitsu/smihandler.c index fe8e70c..1662144 100644 --- a/src/mainboard/intel/kunimitsu/smihandler.c +++ b/src/mainboard/intel/kunimitsu/smihandler.c @@ -28,6 +28,7 @@ #include <soc/pm.h> #include <soc/smm.h> #include "ec.h" +#include "gpio.h"
int mainboard_io_trap_handler(int smif) {