[coreboot-gerrit] [S] Change in coreboot[master]: soc/ti/am335x: Change and optimize memlayout

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70160 )

Change subject: soc/ti/am335x: Change and optimize memlayout
......................................................................

soc/ti/am335x: Change and optimize memlayout

Clang builds are slightly larget than GCC builds so increase the size of
both bootblock and romstage.

The technical reference manual mentions no upper limit to the size of
the bootblock in the TI header so increasing the bootblock size is
allowed.

Change-Id: I8719bc3728d4cc8dba8d939cc154c3fc0884d47b
Signed-off-by: Arthur Heymans 
---
M src/mainboard/ti/beaglebone/board.fmd
M src/soc/ti/am335x/memlayout.ld
2 files changed, 25 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/70160/1

diff --git a/src/mainboard/ti/beaglebone/board.fmd b/src/mainboard/ti/beaglebone/board.fmd
index 0656b85..26a210f 100644
--- a/src/mainboard/ti/beaglebone/board.fmd
+++ b/src/mainboard/ti/beaglebone/board.fmd
@@ -1,6 +1,6 @@
 FLASH@0x000 32M {
     BIOS@0x0 109K {
-        BOOTBLOCK@0x0 20K
+        BOOTBLOCK@0x0 22K
     }

PAYLOAD {
diff --git a/src/soc/ti/am335x/memlayout.ld b/src/soc/ti/am335x/memlayout.ld
index 8d1e8d6..e3e783e 100644
--- a/src/soc/ti/am335x/memlayout.ld
+++ b/src/soc/ti/am335x/memlayout.ld
@@ -7,15 +7,14 @@
 SECTIONS
 {
    SRAM_START(0x402f0400)
-	BOOTBLOCK(0x402f0400, 20K)
-	FMAP_CACHE(0x402f0400+20K, 2K)
-	CBFS_MCACHE(0x402f0400+20K+2K, 8K)
-	TTB(0x402F8000, 16K)
-	ROMSTAGE(0x402F8000+16K, 40K)
+	BOOTBLOCK(., 22K)
+	FMAP_CACHE(., 2K)
+	CBFS_MCACHE(., 8K)
+	ROMSTAGE(., 42K)
+	PRERAM_CBFS_CACHE(., 20K)

-	PRERAM_CBFS_CACHE(0x402F8000+16K+40K, 20K)
-
-	STACK(0x4030be00, 4K)
+	STACK(., 4K)
+	TTB(0x4030c000, 16K)
    SRAM_END(0x40310000)

DRAM_START(0x80000000)