build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31408 )
Change subject: nb/intel/i945: Use big enough type for left-shift ......................................................................
Patch Set 3:
(6 comments)
https://review.coreboot.org/#/c/31408/3/src/northbridge/intel/i945/acpi.c File src/northbridge/intel/i945/acpi.c:
https://review.coreboot.org/#/c/31408/3/src/northbridge/intel/i945/acpi.c@44 PS3, Line 44: pciexbar = pciexbar_reg & ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)); line over 80 characters
https://review.coreboot.org/#/c/31408/3/src/northbridge/intel/i945/acpi.c@48 PS3, Line 48: pciexbar = pciexbar_reg & ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); line over 80 characters
https://review.coreboot.org/#/c/31408/3/src/northbridge/intel/i945/acpi.c@52 PS3, Line 52: pciexbar = pciexbar_reg & ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); line over 80 characters
https://review.coreboot.org/#/c/31408/3/src/northbridge/intel/i945/northbrid... File src/northbridge/intel/i945/northbridge.c:
https://review.coreboot.org/#/c/31408/3/src/northbridge/intel/i945/northbrid... PS3, Line 48: *base = pciexbar_reg & ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)); line over 80 characters
https://review.coreboot.org/#/c/31408/3/src/northbridge/intel/i945/northbrid... PS3, Line 51: *base = pciexbar_reg & ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); line over 80 characters
https://review.coreboot.org/#/c/31408/3/src/northbridge/intel/i945/northbrid... PS3, Line 54: *base = pciexbar_reg & ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); line over 80 characters