Attention is currently required from: Ashish Kumar Mishra, Harsha B R, Rizwan Qureshi, Krishna P Bhat D, Ronak Kanabar, Usha P.
Harsha B R has uploaded a new patch set (#11) to the change originally created by Ashish Kumar Mishra. ( https://review.coreboot.org/c/coreboot/+/69741 )
Change subject: mb/intel/mtlrvp: Add romstage and configure LP5 memory parts ......................................................................
mb/intel/mtlrvp: Add romstage and configure LP5 memory parts
This patch adds initial romstage code and spd data for LP5 memory parts for MTL-RVP. This also configures memory based on the board id.
BUG=b:224325352 TEST=Able to boot to intel/mtlrvp
Signed-off-by: Ashish Kumar Mishra ashish.k.mishra@intel.com Change-Id: I15b352eb246aed23da273e56490c7094eae9d176 Signed-off-by: Harsha B R harsha.b.r@intel.com --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/Makefile.inc M src/mainboard/intel/mtlrvp/romstage_fsp_params.c A src/mainboard/intel/mtlrvp/spd/Makefile.inc A src/mainboard/intel/mtlrvp/spd/empty.spd.hex A src/mainboard/intel/mtlrvp/spd/hynix_mtlrvp_lp5.spd.hex A src/mainboard/intel/mtlrvp/spd/micron_mtlrvp_lp5.spd.hex M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/memory.c 8 files changed, 208 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/69741/11