Hello build bot (Jenkins), Jingle Hsu, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45941
to look at the new patch set (#6).
Change subject: soc/intel/xeon_sp/cpx: correct GSI bases for IO APICs ......................................................................
soc/intel/xeon_sp/cpx: correct GSI bases for IO APICs
With CPX-SP FSP, PCH IOAPIC handles the first 120(0x78) GSIs. Correct the coreboot assignment of GSIs for IO APICs.
Without this patch, there are following target OS boot messages: [ 1.098771] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119 [ 1.099159] GSI range [24-31] for new IOAPIC conflicts with GSI[0-119]
After this patch, the boot messages are: [ 0.399498] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119 [ 0.399848] IOAPIC[1]: apic_id 9, version 32, address 0xfec01000, GSI 120-127
Also without this patch, there is boot stability issue. About one in 20 reboots, the target OS fails to boot with following failure: [ 4.325795] mce: [Hardware Error]: Machine check events logged [ 4.326597] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 9: ee2000000003110a [ 4.327594] mce: [Hardware Error]: TSC 0 ADDR fe9e0000 MISC 228aa040101086 [ 4.328596] mce: [Hardware Error]: PROCESSOR 0:5065b TIME 1601443875 SOCKET 0 APIC 0 microcode 700001d
The MCE error happens in bank 9. The Model specific error code shows it is about SAD_ERR_WB_TO_MMIO error (doc 604926), which means something goes wrong when cache write back to mmio. It is a generic transaction type error in level 2.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I45e941591300dad6d583a6dcb41f45e984753c07 --- M src/soc/intel/xeon_sp/cpx/acpi.c 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/45941/6