Alexandru Gagniuc (mr.nuke.me@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8477
-gerrit
commit dde0cd274236717e17e27f02c728e1e063baa28c Author: Alexandru Gagniuc mr.nuke.me@gmail.com Date: Sun Feb 15 14:09:21 2015 -0600
google/butterfly: Drop MRC.bin in favor of native raminit
I thought this wasn't going to work, and observing the timC detection failure of early tests, I was getting somewhat discouraged; however, this works. I've tried it with all possible permutations of the following memory modules: * 2 GiB single-rank DDR3-1600 * 4 GiB single-rank DDR3-1600 * 4 GiB dual-rank DDR3-1600
I did notice a limited number of memtest errors during one of the runs, but they were in an address range that is otherwise marked as reserved. I wrote that off as "maybe something was doing MMIO there just when memtest was poking the address range". I was not able to reproduce that error.
Change-Id: Ibd52e1d52fc8d900591d6a488f9a5b4d1e5e4fd3 Signed-off-by: Alexandru Gagniuc mr.nuke.me@gmail.com --- src/mainboard/google/butterfly/Kconfig | 2 +- src/mainboard/google/butterfly/Makefile.inc | 1 + src/mainboard/google/butterfly/devicetree.cb | 2 + src/mainboard/google/butterfly/gpio.c | 300 ++++++++++++++++++++++++++ src/mainboard/google/butterfly/gpio.h | 304 --------------------------- src/mainboard/google/butterfly/romstage.c | 159 +++----------- 6 files changed, 328 insertions(+), 440 deletions(-)
diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index df7460a..811a9fe 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE select SOUTHBRIDGE_INTEL_C216 select EC_QUANTA_ENE_KB3940Q select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index f735e9c..456528e 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -21,5 +21,6 @@ ramstage-y += ec.c
romstage-y += chromeos.c ramstage-y += chromeos.c +romstage-y += gpio.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index ed0d8d1..90925b9 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -12,6 +12,8 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
+ register "max_mem_clock_mhz" = "666" # DDR3-1333 + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end diff --git a/src/mainboard/google/butterfly/gpio.c b/src/mainboard/google/butterfly/gpio.c new file mode 100644 index 0000000..5d997c7 --- /dev/null +++ b/src/mainboard/google/butterfly/gpio.c @@ -0,0 +1,300 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "southbridge/intel/bd82x6x/gpio.h" + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NONE, /* Unused */ + .gpio1 = GPIO_MODE_NONE, /* Unused */ + .gpio2 = GPIO_MODE_NONE, /* Unused */ + .gpio3 = GPIO_MODE_NONE, /* Unused */ + .gpio4 = GPIO_MODE_NATIVE, /* Native - TPSINT# for TP SMBus IRQ */ + .gpio5 = GPIO_MODE_NONE, /* Unused */ + .gpio6 = GPIO_MODE_GPIO, /* Input - BOARD_ID4 */ + .gpio7 = GPIO_MODE_GPIO, /* Input - BOARD_ID5 */ + .gpio8 = GPIO_MODE_GPIO, /* Output - BT on/off */ + .gpio9 = GPIO_MODE_NONE, /* Unused */ + .gpio10 = GPIO_MODE_NONE, /* Unused */ + .gpio11 = GPIO_MODE_GPIO, /* Input - TP WAKEUP Event */ + .gpio12 = GPIO_MODE_NONE, /* Unused */ + .gpio13 = GPIO_MODE_GPIO, /* Input - SCI from EC */ + .gpio14 = GPIO_MODE_GPIO, /* Output - AOAC WLAN power control */ + .gpio15 = GPIO_MODE_GPIO, /* Unused - Do not control WLAN*/ + .gpio16 = GPIO_MODE_NONE, /* Unused */ + .gpio17 = GPIO_MODE_GPIO, /* Input - DGPU_PWROK */ + .gpio18 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ1# LAN clock pin*/ + .gpio19 = GPIO_MODE_GPIO, /* Input - Boot BIOS Selection 0 */ + .gpio20 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ2# SDCard clock pin */ + .gpio21 = GPIO_MODE_GPIO, /* Input - EC_ENTERING_RW for Google OS */ + .gpio22 = GPIO_MODE_GPIO, /* Input - BIOS RECOVERY */ + .gpio23 = GPIO_MODE_NONE, /* Unused */ + .gpio24 = GPIO_MODE_GPIO, /* Output - DGPU_HOLD_RST# */ + .gpio25 = GPIO_MODE_NONE, /* Unused */ + .gpio26 = GPIO_MODE_NONE, /* Unused */ + .gpio27 = GPIO_MODE_NONE, /* Unused */ + .gpio28 = GPIO_MODE_NONE, /* Unused */ + .gpio29 = GPIO_MODE_NONE, /* Unused */ + .gpio30 = GPIO_MODE_NATIVE, /* Native - SUSWARN_EC# */ + .gpio31 = GPIO_MODE_NONE, /* Unused */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, /* Unused */ + .gpio1 = GPIO_DIR_INPUT, /* Unused */ + .gpio2 = GPIO_DIR_INPUT, /* Unused */ + .gpio3 = GPIO_DIR_INPUT, /* Unused */ + .gpio4 = GPIO_DIR_INPUT, /* Native */ + .gpio5 = GPIO_DIR_INPUT, /* Unused */ + .gpio6 = GPIO_DIR_INPUT, /* Input */ + .gpio7 = GPIO_DIR_INPUT, /* Input */ + .gpio8 = GPIO_DIR_INPUT, /* Output HIGH - set in mainboard.c */ + .gpio9 = GPIO_DIR_INPUT, /* Unused */ + .gpio10 = GPIO_DIR_INPUT, /* Unused */ + .gpio11 = GPIO_DIR_INPUT, /* Input */ + .gpio12 = GPIO_DIR_INPUT, /* Unused */ + .gpio13 = GPIO_DIR_INPUT, /* Input */ + .gpio14 = GPIO_DIR_OUTPUT, /* Output HIGH */ + .gpio15 = GPIO_DIR_INPUT, /* Unused */ + .gpio16 = GPIO_DIR_INPUT, /* Unused */ + .gpio17 = GPIO_DIR_INPUT, /* Input */ + .gpio18 = GPIO_DIR_INPUT, /* Native */ + .gpio19 = GPIO_DIR_INPUT, /* Input */ + .gpio20 = GPIO_DIR_INPUT, /* Native */ + .gpio21 = GPIO_DIR_INPUT, /* Input */ + .gpio22 = GPIO_DIR_INPUT, /* Input */ + .gpio23 = GPIO_DIR_INPUT, /* Unused */ + .gpio24 = GPIO_DIR_OUTPUT, /* Output HIGH */ + .gpio25 = GPIO_DIR_INPUT, /* Unused */ + .gpio26 = GPIO_DIR_INPUT, /* Unused */ + .gpio27 = GPIO_DIR_INPUT, /* Unused */ + .gpio28 = GPIO_DIR_INPUT, /* Unused */ + .gpio29 = GPIO_DIR_INPUT, /* Unused */ + .gpio30 = GPIO_DIR_INPUT, /* Native */ + .gpio31 = GPIO_DIR_INPUT, /* Unused */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, /* Unused */ + .gpio1 = GPIO_LEVEL_LOW, /* Unused */ + .gpio2 = GPIO_LEVEL_LOW, /* Unused */ + .gpio3 = GPIO_LEVEL_LOW, /* Unused */ + .gpio4 = GPIO_LEVEL_LOW, /* Native */ + .gpio5 = GPIO_LEVEL_LOW, /* Unused */ + .gpio6 = GPIO_LEVEL_LOW, /* Input */ + .gpio7 = GPIO_LEVEL_LOW, /* Input */ + .gpio8 = GPIO_LEVEL_HIGH, /* Output HIGH - set in mainboard.c */ + .gpio9 = GPIO_LEVEL_LOW, /* Unused */ + .gpio10 = GPIO_LEVEL_LOW, /* Unused */ + .gpio11 = GPIO_LEVEL_LOW, /* Input */ + .gpio12 = GPIO_LEVEL_LOW, /* Unused */ + .gpio13 = GPIO_LEVEL_LOW, /* Input */ + .gpio14 = GPIO_LEVEL_HIGH, /* Output HIGH */ + .gpio15 = GPIO_LEVEL_HIGH, /* Unused */ + .gpio16 = GPIO_LEVEL_LOW, /* Unused */ + .gpio17 = GPIO_LEVEL_LOW, /* Input */ + .gpio18 = GPIO_LEVEL_LOW, /* Native */ + .gpio19 = GPIO_LEVEL_LOW, /* Input */ + .gpio20 = GPIO_LEVEL_LOW, /* Native */ + .gpio21 = GPIO_LEVEL_LOW, /* Input */ + .gpio22 = GPIO_LEVEL_LOW, /* Input */ + .gpio23 = GPIO_LEVEL_LOW, /* Unused */ + .gpio24 = GPIO_LEVEL_HIGH, /* Output HIGH */ + .gpio25 = GPIO_LEVEL_LOW, /* Unused */ + .gpio26 = GPIO_LEVEL_LOW, /* Unused */ + .gpio27 = GPIO_LEVEL_LOW, /* Unused */ + .gpio28 = GPIO_LEVEL_LOW, /* Unused */ + .gpio29 = GPIO_LEVEL_LOW, /* Unused */ + .gpio30 = GPIO_LEVEL_LOW, /* Native */ + .gpio31 = GPIO_LEVEL_LOW, /* Unused */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio11 = GPIO_INVERT, /* invert touchpad wakeup pin */ + .gpio13 = GPIO_INVERT, /* invert EC SCI pin */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, /* Native - Connect to EC Clock Run */ + .gpio33 = GPIO_MODE_GPIO, /* Input - (Google protect BIOS ROM) */ + .gpio34 = GPIO_MODE_NONE, /* Unused */ + .gpio35 = GPIO_MODE_NONE, /* Unused */ + .gpio36 = GPIO_MODE_GPIO, /* Output - DGPU_PWR_EN */ + .gpio37 = GPIO_MODE_GPIO, /* Input - FDI TERM / VOLTAGE OVERRIDE */ + .gpio38 = GPIO_MODE_GPIO, /* Input - MFG_MODE test */ + .gpio39 = GPIO_MODE_GPIO, /* Input - DGPU_PRSNT */ + .gpio40 = GPIO_MODE_NONE, /* Unused */ + .gpio41 = GPIO_MODE_NONE, /* Unused */ + .gpio42 = GPIO_MODE_NONE, /* Unused */ + .gpio43 = GPIO_MODE_NONE, /* Unused */ + .gpio44 = GPIO_MODE_GPIO, /* Input - BOARD_ID0 */ + .gpio45 = GPIO_MODE_GPIO, /* Input - BOARD_ID1 */ + .gpio46 = GPIO_MODE_GPIO, /* Input - BOARD_ID2 */ + .gpio47 = GPIO_MODE_NATIVE, /* Native - PEGA_GPU clock request */ + .gpio48 = GPIO_MODE_NONE, /* Unused */ + .gpio49 = GPIO_MODE_NONE, /* Unused */ + .gpio50 = GPIO_MODE_NONE, /* Unused */ + .gpio51 = GPIO_MODE_GPIO, /* Input - Boot BIOS Selection 1 */ + .gpio52 = GPIO_MODE_GPIO, /* Input - Google recovery, Pull up +3V */ + .gpio53 = GPIO_MODE_GPIO, /* Output - G Sensor LED */ + .gpio54 = GPIO_MODE_GPIO, /* Input - Google Development */ + .gpio55 = GPIO_MODE_GPIO, /* Input - Top-Block Swap Override */ + .gpio56 = GPIO_MODE_NONE, /* Unused */ + .gpio57 = GPIO_MODE_GPIO, /* Input - SV_DET */ + .gpio58 = GPIO_MODE_NONE, /* Unused */ + .gpio59 = GPIO_MODE_NONE, /* Unused */ + .gpio60 = GPIO_MODE_NONE, /* GPO - DRAMRST_CNTRL_PCH */ + .gpio61 = GPIO_MODE_NONE, /* Unused */ + .gpio62 = GPIO_MODE_NATIVE, /* Native - Connect to EC 32.768KHz */ + .gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5 */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, /* Native */ + .gpio33 = GPIO_DIR_INPUT, /* Input */ + .gpio34 = GPIO_DIR_INPUT, /* Unused */ + .gpio35 = GPIO_DIR_INPUT, /* Unused */ + .gpio36 = GPIO_DIR_OUTPUT, /* Output HIGH */ + .gpio37 = GPIO_DIR_INPUT, /* Input */ + .gpio38 = GPIO_DIR_INPUT, /* Input */ + .gpio39 = GPIO_DIR_INPUT, /* Input */ + .gpio40 = GPIO_DIR_INPUT, /* Unused */ + .gpio41 = GPIO_DIR_INPUT, /* Unused */ + .gpio42 = GPIO_DIR_INPUT, /* Unused */ + .gpio43 = GPIO_DIR_INPUT, /* Unused */ + .gpio44 = GPIO_DIR_INPUT, /* Input */ + .gpio45 = GPIO_DIR_INPUT, /* Input */ + .gpio46 = GPIO_DIR_INPUT, /* Input */ + .gpio47 = GPIO_DIR_INPUT, /* Native */ + .gpio48 = GPIO_DIR_INPUT, /* Unused */ + .gpio49 = GPIO_DIR_INPUT, /* Unused */ + .gpio50 = GPIO_DIR_INPUT, /* Unused */ + .gpio51 = GPIO_DIR_INPUT, /* Input */ + .gpio52 = GPIO_DIR_INPUT, /* Input */ + .gpio53 = GPIO_DIR_OUTPUT, /* Input */ + .gpio54 = GPIO_DIR_INPUT, /* Input */ + .gpio55 = GPIO_DIR_INPUT, /* Input */ + .gpio56 = GPIO_DIR_INPUT, /* Unused */ + .gpio57 = GPIO_DIR_INPUT, /* Input */ + .gpio58 = GPIO_DIR_INPUT, /* Unused */ + .gpio59 = GPIO_DIR_INPUT, /* Unused */ + .gpio60 = GPIO_DIR_OUTPUT, /* Output HIGH */ + .gpio61 = GPIO_DIR_INPUT, /* Unused */ + .gpio62 = GPIO_DIR_INPUT, /* Native */ + .gpio63 = GPIO_DIR_INPUT, /* Native */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, /* Native */ + .gpio33 = GPIO_LEVEL_LOW, /* Input */ + .gpio34 = GPIO_LEVEL_LOW, /* Unused */ + .gpio35 = GPIO_LEVEL_LOW, /* Unused */ + .gpio36 = GPIO_LEVEL_HIGH, /* Output HIGH */ + .gpio37 = GPIO_LEVEL_LOW, /* Input */ + .gpio38 = GPIO_LEVEL_LOW, /* Input */ + .gpio39 = GPIO_LEVEL_LOW, /* Input */ + .gpio40 = GPIO_LEVEL_LOW, /* Unused */ + .gpio41 = GPIO_LEVEL_LOW, /* Unused */ + .gpio42 = GPIO_LEVEL_LOW, /* Unused */ + .gpio43 = GPIO_LEVEL_LOW, /* Unused */ + .gpio44 = GPIO_LEVEL_LOW, /* Input */ + .gpio45 = GPIO_LEVEL_LOW, /* Input */ + .gpio46 = GPIO_LEVEL_LOW, /* Input */ + .gpio47 = GPIO_LEVEL_LOW, /* Native */ + .gpio48 = GPIO_LEVEL_LOW, /* Unused */ + .gpio49 = GPIO_LEVEL_LOW, /* Unused */ + .gpio50 = GPIO_LEVEL_LOW, /* Unused */ + .gpio51 = GPIO_LEVEL_LOW, /* Input */ + .gpio52 = GPIO_LEVEL_LOW, /* Input */ + .gpio53 = GPIO_LEVEL_HIGH, /* Input */ + .gpio54 = GPIO_LEVEL_LOW, /* Input */ + .gpio55 = GPIO_LEVEL_LOW, /* Input */ + .gpio56 = GPIO_LEVEL_LOW, /* Unused */ + .gpio57 = GPIO_LEVEL_LOW, /* Input */ + .gpio58 = GPIO_LEVEL_LOW, /* Unused */ + .gpio59 = GPIO_LEVEL_LOW, /* Unused */ + .gpio60 = GPIO_LEVEL_HIGH, /* Output HIGH */ + .gpio61 = GPIO_LEVEL_LOW, /* Unused */ + .gpio62 = GPIO_LEVEL_LOW, /* Native */ + .gpio63 = GPIO_LEVEL_LOW, /* Native */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NONE, /* Unused */ + .gpio65 = GPIO_MODE_NONE, /* Unused */ + .gpio66 = GPIO_MODE_NONE, /* Unused */ + .gpio67 = GPIO_MODE_NONE, /* Unused */ + .gpio68 = GPIO_MODE_GPIO, /* Input - DGPU_PWR_EN */ + .gpio69 = GPIO_MODE_NONE, /* Unused */ + .gpio70 = GPIO_MODE_NONE, /* Unused */ + .gpio71 = GPIO_MODE_NONE, /* Unused */ + .gpio72 = GPIO_MODE_NONE, /* Unused */ + .gpio73 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ0# WLAN clock request */ + .gpio74 = GPIO_MODE_NONE, /* Unused */ + .gpio75 = GPIO_MODE_GPIO, /* Input - SMB_ME1_DAT */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, /* Unused */ + .gpio65 = GPIO_DIR_INPUT, /* Unused */ + .gpio66 = GPIO_DIR_INPUT, /* Unused */ + .gpio67 = GPIO_DIR_INPUT, /* Unused */ + .gpio68 = GPIO_DIR_INPUT, /* Input */ + .gpio69 = GPIO_DIR_INPUT, /* Unused */ + .gpio70 = GPIO_DIR_INPUT, /* Unused */ + .gpio71 = GPIO_DIR_INPUT, /* Unused */ + .gpio72 = GPIO_DIR_INPUT, /* Unused */ + .gpio73 = GPIO_DIR_INPUT, /* Native */ + .gpio74 = GPIO_DIR_INPUT, /* Unused */ + .gpio75 = GPIO_DIR_INPUT, /* Input */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, /* Unused */ + .gpio65 = GPIO_LEVEL_LOW, /* Unused */ + .gpio66 = GPIO_LEVEL_LOW, /* Unused */ + .gpio67 = GPIO_LEVEL_LOW, /* Unused */ + .gpio68 = GPIO_LEVEL_LOW, /* Input */ + .gpio69 = GPIO_LEVEL_LOW, /* Unused */ + .gpio70 = GPIO_LEVEL_LOW, /* Unused */ + .gpio71 = GPIO_LEVEL_LOW, /* Unused */ + .gpio72 = GPIO_LEVEL_LOW, /* Unused */ + .gpio73 = GPIO_LEVEL_LOW, /* Native */ + .gpio74 = GPIO_LEVEL_LOW, /* Unused */ + .gpio75 = GPIO_LEVEL_LOW, /* Input */ +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; diff --git a/src/mainboard/google/butterfly/gpio.h b/src/mainboard/google/butterfly/gpio.h deleted file mode 100644 index b592e6a..0000000 --- a/src/mainboard/google/butterfly/gpio.h +++ /dev/null @@ -1,304 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef BUTTERFLY_GPIO_H -#define BUTTERFLY_GPIO_H - -#include "southbridge/intel/bd82x6x/gpio.h" - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_NONE, /* Unused */ - .gpio1 = GPIO_MODE_NONE, /* Unused */ - .gpio2 = GPIO_MODE_NONE, /* Unused */ - .gpio3 = GPIO_MODE_NONE, /* Unused */ - .gpio4 = GPIO_MODE_NATIVE, /* Native - TPSINT# for TP SMBus IRQ */ - .gpio5 = GPIO_MODE_NONE, /* Unused */ - .gpio6 = GPIO_MODE_GPIO, /* Input - BOARD_ID4 */ - .gpio7 = GPIO_MODE_GPIO, /* Input - BOARD_ID5 */ - .gpio8 = GPIO_MODE_GPIO, /* Output - BT on/off */ - .gpio9 = GPIO_MODE_NONE, /* Unused */ - .gpio10 = GPIO_MODE_NONE, /* Unused */ - .gpio11 = GPIO_MODE_GPIO, /* Input - TP WAKEUP Event */ - .gpio12 = GPIO_MODE_NONE, /* Unused */ - .gpio13 = GPIO_MODE_GPIO, /* Input - SCI from EC */ - .gpio14 = GPIO_MODE_GPIO, /* Output - AOAC WLAN power control */ - .gpio15 = GPIO_MODE_GPIO, /* Unused - Do not control WLAN*/ - .gpio16 = GPIO_MODE_NONE, /* Unused */ - .gpio17 = GPIO_MODE_GPIO, /* Input - DGPU_PWROK */ - .gpio18 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ1# LAN clock pin*/ - .gpio19 = GPIO_MODE_GPIO, /* Input - Boot BIOS Selection 0 */ - .gpio20 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ2# SDCard clock pin */ - .gpio21 = GPIO_MODE_GPIO, /* Input - EC_ENTERING_RW for Google OS */ - .gpio22 = GPIO_MODE_GPIO, /* Input - BIOS RECOVERY */ - .gpio23 = GPIO_MODE_NONE, /* Unused */ - .gpio24 = GPIO_MODE_GPIO, /* Output - DGPU_HOLD_RST# */ - .gpio25 = GPIO_MODE_NONE, /* Unused */ - .gpio26 = GPIO_MODE_NONE, /* Unused */ - .gpio27 = GPIO_MODE_NONE, /* Unused */ - .gpio28 = GPIO_MODE_NONE, /* Unused */ - .gpio29 = GPIO_MODE_NONE, /* Unused */ - .gpio30 = GPIO_MODE_NATIVE, /* Native - SUSWARN_EC# */ - .gpio31 = GPIO_MODE_NONE, /* Unused */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, /* Unused */ - .gpio1 = GPIO_DIR_INPUT, /* Unused */ - .gpio2 = GPIO_DIR_INPUT, /* Unused */ - .gpio3 = GPIO_DIR_INPUT, /* Unused */ - .gpio4 = GPIO_DIR_INPUT, /* Native */ - .gpio5 = GPIO_DIR_INPUT, /* Unused */ - .gpio6 = GPIO_DIR_INPUT, /* Input */ - .gpio7 = GPIO_DIR_INPUT, /* Input */ - .gpio8 = GPIO_DIR_INPUT, /* Output HIGH - set in mainboard.c */ - .gpio9 = GPIO_DIR_INPUT, /* Unused */ - .gpio10 = GPIO_DIR_INPUT, /* Unused */ - .gpio11 = GPIO_DIR_INPUT, /* Input */ - .gpio12 = GPIO_DIR_INPUT, /* Unused */ - .gpio13 = GPIO_DIR_INPUT, /* Input */ - .gpio14 = GPIO_DIR_OUTPUT, /* Output HIGH */ - .gpio15 = GPIO_DIR_INPUT, /* Unused */ - .gpio16 = GPIO_DIR_INPUT, /* Unused */ - .gpio17 = GPIO_DIR_INPUT, /* Input */ - .gpio18 = GPIO_DIR_INPUT, /* Native */ - .gpio19 = GPIO_DIR_INPUT, /* Input */ - .gpio20 = GPIO_DIR_INPUT, /* Native */ - .gpio21 = GPIO_DIR_INPUT, /* Input */ - .gpio22 = GPIO_DIR_INPUT, /* Input */ - .gpio23 = GPIO_DIR_INPUT, /* Unused */ - .gpio24 = GPIO_DIR_OUTPUT, /* Output HIGH */ - .gpio25 = GPIO_DIR_INPUT, /* Unused */ - .gpio26 = GPIO_DIR_INPUT, /* Unused */ - .gpio27 = GPIO_DIR_INPUT, /* Unused */ - .gpio28 = GPIO_DIR_INPUT, /* Unused */ - .gpio29 = GPIO_DIR_INPUT, /* Unused */ - .gpio30 = GPIO_DIR_INPUT, /* Native */ - .gpio31 = GPIO_DIR_INPUT, /* Unused */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_LOW, /* Unused */ - .gpio1 = GPIO_LEVEL_LOW, /* Unused */ - .gpio2 = GPIO_LEVEL_LOW, /* Unused */ - .gpio3 = GPIO_LEVEL_LOW, /* Unused */ - .gpio4 = GPIO_LEVEL_LOW, /* Native */ - .gpio5 = GPIO_LEVEL_LOW, /* Unused */ - .gpio6 = GPIO_LEVEL_LOW, /* Input */ - .gpio7 = GPIO_LEVEL_LOW, /* Input */ - .gpio8 = GPIO_LEVEL_HIGH, /* Output HIGH - set in mainboard.c */ - .gpio9 = GPIO_LEVEL_LOW, /* Unused */ - .gpio10 = GPIO_LEVEL_LOW, /* Unused */ - .gpio11 = GPIO_LEVEL_LOW, /* Input */ - .gpio12 = GPIO_LEVEL_LOW, /* Unused */ - .gpio13 = GPIO_LEVEL_LOW, /* Input */ - .gpio14 = GPIO_LEVEL_HIGH, /* Output HIGH */ - .gpio15 = GPIO_LEVEL_HIGH, /* Unused */ - .gpio16 = GPIO_LEVEL_LOW, /* Unused */ - .gpio17 = GPIO_LEVEL_LOW, /* Input */ - .gpio18 = GPIO_LEVEL_LOW, /* Native */ - .gpio19 = GPIO_LEVEL_LOW, /* Input */ - .gpio20 = GPIO_LEVEL_LOW, /* Native */ - .gpio21 = GPIO_LEVEL_LOW, /* Input */ - .gpio22 = GPIO_LEVEL_LOW, /* Input */ - .gpio23 = GPIO_LEVEL_LOW, /* Unused */ - .gpio24 = GPIO_LEVEL_HIGH, /* Output HIGH */ - .gpio25 = GPIO_LEVEL_LOW, /* Unused */ - .gpio26 = GPIO_LEVEL_LOW, /* Unused */ - .gpio27 = GPIO_LEVEL_LOW, /* Unused */ - .gpio28 = GPIO_LEVEL_LOW, /* Unused */ - .gpio29 = GPIO_LEVEL_LOW, /* Unused */ - .gpio30 = GPIO_LEVEL_LOW, /* Native */ - .gpio31 = GPIO_LEVEL_LOW, /* Unused */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio11 = GPIO_INVERT, /* invert touchpad wakeup pin */ - .gpio13 = GPIO_INVERT, /* invert EC SCI pin */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, /* Native - Connect to EC Clock Run */ - .gpio33 = GPIO_MODE_GPIO, /* Input - (Google protect BIOS ROM) */ - .gpio34 = GPIO_MODE_NONE, /* Unused */ - .gpio35 = GPIO_MODE_NONE, /* Unused */ - .gpio36 = GPIO_MODE_GPIO, /* Output - DGPU_PWR_EN */ - .gpio37 = GPIO_MODE_GPIO, /* Input - FDI TERM / VOLTAGE OVERRIDE */ - .gpio38 = GPIO_MODE_GPIO, /* Input - MFG_MODE test */ - .gpio39 = GPIO_MODE_GPIO, /* Input - DGPU_PRSNT */ - .gpio40 = GPIO_MODE_NONE, /* Unused */ - .gpio41 = GPIO_MODE_NONE, /* Unused */ - .gpio42 = GPIO_MODE_NONE, /* Unused */ - .gpio43 = GPIO_MODE_NONE, /* Unused */ - .gpio44 = GPIO_MODE_GPIO, /* Input - BOARD_ID0 */ - .gpio45 = GPIO_MODE_GPIO, /* Input - BOARD_ID1 */ - .gpio46 = GPIO_MODE_GPIO, /* Input - BOARD_ID2 */ - .gpio47 = GPIO_MODE_NATIVE, /* Native - PEGA_GPU clock request */ - .gpio48 = GPIO_MODE_NONE, /* Unused */ - .gpio49 = GPIO_MODE_NONE, /* Unused */ - .gpio50 = GPIO_MODE_NONE, /* Unused */ - .gpio51 = GPIO_MODE_GPIO, /* Input - Boot BIOS Selection 1 */ - .gpio52 = GPIO_MODE_GPIO, /* Input - Google recovery, Pull up +3V */ - .gpio53 = GPIO_MODE_GPIO, /* Output - G Sensor LED */ - .gpio54 = GPIO_MODE_GPIO, /* Input - Google Development */ - .gpio55 = GPIO_MODE_GPIO, /* Input - Top-Block Swap Override */ - .gpio56 = GPIO_MODE_NONE, /* Unused */ - .gpio57 = GPIO_MODE_GPIO, /* Input - SV_DET */ - .gpio58 = GPIO_MODE_NONE, /* Unused */ - .gpio59 = GPIO_MODE_NONE, /* Unused */ - .gpio60 = GPIO_MODE_NONE, /* GPO - DRAMRST_CNTRL_PCH */ - .gpio61 = GPIO_MODE_NONE, /* Unused */ - .gpio62 = GPIO_MODE_NATIVE, /* Native - Connect to EC 32.768KHz */ - .gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5 */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_INPUT, /* Native */ - .gpio33 = GPIO_DIR_INPUT, /* Input */ - .gpio34 = GPIO_DIR_INPUT, /* Unused */ - .gpio35 = GPIO_DIR_INPUT, /* Unused */ - .gpio36 = GPIO_DIR_OUTPUT, /* Output HIGH */ - .gpio37 = GPIO_DIR_INPUT, /* Input */ - .gpio38 = GPIO_DIR_INPUT, /* Input */ - .gpio39 = GPIO_DIR_INPUT, /* Input */ - .gpio40 = GPIO_DIR_INPUT, /* Unused */ - .gpio41 = GPIO_DIR_INPUT, /* Unused */ - .gpio42 = GPIO_DIR_INPUT, /* Unused */ - .gpio43 = GPIO_DIR_INPUT, /* Unused */ - .gpio44 = GPIO_DIR_INPUT, /* Input */ - .gpio45 = GPIO_DIR_INPUT, /* Input */ - .gpio46 = GPIO_DIR_INPUT, /* Input */ - .gpio47 = GPIO_DIR_INPUT, /* Native */ - .gpio48 = GPIO_DIR_INPUT, /* Unused */ - .gpio49 = GPIO_DIR_INPUT, /* Unused */ - .gpio50 = GPIO_DIR_INPUT, /* Unused */ - .gpio51 = GPIO_DIR_INPUT, /* Input */ - .gpio52 = GPIO_DIR_INPUT, /* Input */ - .gpio53 = GPIO_DIR_OUTPUT, /* Input */ - .gpio54 = GPIO_DIR_INPUT, /* Input */ - .gpio55 = GPIO_DIR_INPUT, /* Input */ - .gpio56 = GPIO_DIR_INPUT, /* Unused */ - .gpio57 = GPIO_DIR_INPUT, /* Input */ - .gpio58 = GPIO_DIR_INPUT, /* Unused */ - .gpio59 = GPIO_DIR_INPUT, /* Unused */ - .gpio60 = GPIO_DIR_OUTPUT, /* Output HIGH */ - .gpio61 = GPIO_DIR_INPUT, /* Unused */ - .gpio62 = GPIO_DIR_INPUT, /* Native */ - .gpio63 = GPIO_DIR_INPUT, /* Native */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_LOW, /* Native */ - .gpio33 = GPIO_LEVEL_LOW, /* Input */ - .gpio34 = GPIO_LEVEL_LOW, /* Unused */ - .gpio35 = GPIO_LEVEL_LOW, /* Unused */ - .gpio36 = GPIO_LEVEL_HIGH, /* Output HIGH */ - .gpio37 = GPIO_LEVEL_LOW, /* Input */ - .gpio38 = GPIO_LEVEL_LOW, /* Input */ - .gpio39 = GPIO_LEVEL_LOW, /* Input */ - .gpio40 = GPIO_LEVEL_LOW, /* Unused */ - .gpio41 = GPIO_LEVEL_LOW, /* Unused */ - .gpio42 = GPIO_LEVEL_LOW, /* Unused */ - .gpio43 = GPIO_LEVEL_LOW, /* Unused */ - .gpio44 = GPIO_LEVEL_LOW, /* Input */ - .gpio45 = GPIO_LEVEL_LOW, /* Input */ - .gpio46 = GPIO_LEVEL_LOW, /* Input */ - .gpio47 = GPIO_LEVEL_LOW, /* Native */ - .gpio48 = GPIO_LEVEL_LOW, /* Unused */ - .gpio49 = GPIO_LEVEL_LOW, /* Unused */ - .gpio50 = GPIO_LEVEL_LOW, /* Unused */ - .gpio51 = GPIO_LEVEL_LOW, /* Input */ - .gpio52 = GPIO_LEVEL_LOW, /* Input */ - .gpio53 = GPIO_LEVEL_HIGH, /* Input */ - .gpio54 = GPIO_LEVEL_LOW, /* Input */ - .gpio55 = GPIO_LEVEL_LOW, /* Input */ - .gpio56 = GPIO_LEVEL_LOW, /* Unused */ - .gpio57 = GPIO_LEVEL_LOW, /* Input */ - .gpio58 = GPIO_LEVEL_LOW, /* Unused */ - .gpio59 = GPIO_LEVEL_LOW, /* Unused */ - .gpio60 = GPIO_LEVEL_HIGH, /* Output HIGH */ - .gpio61 = GPIO_LEVEL_LOW, /* Unused */ - .gpio62 = GPIO_LEVEL_LOW, /* Native */ - .gpio63 = GPIO_LEVEL_LOW, /* Native */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_NONE, /* Unused */ - .gpio65 = GPIO_MODE_NONE, /* Unused */ - .gpio66 = GPIO_MODE_NONE, /* Unused */ - .gpio67 = GPIO_MODE_NONE, /* Unused */ - .gpio68 = GPIO_MODE_GPIO, /* Input - DGPU_PWR_EN */ - .gpio69 = GPIO_MODE_NONE, /* Unused */ - .gpio70 = GPIO_MODE_NONE, /* Unused */ - .gpio71 = GPIO_MODE_NONE, /* Unused */ - .gpio72 = GPIO_MODE_NONE, /* Unused */ - .gpio73 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ0# WLAN clock request */ - .gpio74 = GPIO_MODE_NONE, /* Unused */ - .gpio75 = GPIO_MODE_GPIO, /* Input - SMB_ME1_DAT */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_INPUT, /* Unused */ - .gpio65 = GPIO_DIR_INPUT, /* Unused */ - .gpio66 = GPIO_DIR_INPUT, /* Unused */ - .gpio67 = GPIO_DIR_INPUT, /* Unused */ - .gpio68 = GPIO_DIR_INPUT, /* Input */ - .gpio69 = GPIO_DIR_INPUT, /* Unused */ - .gpio70 = GPIO_DIR_INPUT, /* Unused */ - .gpio71 = GPIO_DIR_INPUT, /* Unused */ - .gpio72 = GPIO_DIR_INPUT, /* Unused */ - .gpio73 = GPIO_DIR_INPUT, /* Native */ - .gpio74 = GPIO_DIR_INPUT, /* Unused */ - .gpio75 = GPIO_DIR_INPUT, /* Input */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { - .gpio64 = GPIO_LEVEL_LOW, /* Unused */ - .gpio65 = GPIO_LEVEL_LOW, /* Unused */ - .gpio66 = GPIO_LEVEL_LOW, /* Unused */ - .gpio67 = GPIO_LEVEL_LOW, /* Unused */ - .gpio68 = GPIO_LEVEL_LOW, /* Input */ - .gpio69 = GPIO_LEVEL_LOW, /* Unused */ - .gpio70 = GPIO_LEVEL_LOW, /* Unused */ - .gpio71 = GPIO_LEVEL_LOW, /* Unused */ - .gpio72 = GPIO_LEVEL_LOW, /* Unused */ - .gpio73 = GPIO_LEVEL_LOW, /* Native */ - .gpio74 = GPIO_LEVEL_LOW, /* Unused */ - .gpio75 = GPIO_LEVEL_LOW, /* Input */ -}; - -const struct pch_gpio_map butterfly_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .invert = &pch_gpio_set1_invert, - - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; -#endif diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index b117295..7f9ab60 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -32,20 +32,18 @@ #include <cbmem.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> -#include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <halt.h> -#include "gpio.h" #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> #endif #include <cbfs.h>
-static void pch_enable_lpc(void) +void pch_enable_lpc(void) { /* EC Decode Range Port60/64 and Port62/66 */ /* Enable EC and PS/2 Keyboard/Mouse*/ @@ -59,7 +57,7 @@ static void pch_enable_lpc(void)
}
-static void rcba_config(void) +void rcba_config(void) { u32 reg32;
@@ -73,134 +71,25 @@ static void rcba_config(void) RCBA32(FD) = reg32; }
-#include <cpu/intel/romstage.h> -void main(unsigned long bist) -{ - int boot_mode = 0; - int cbmem_was_initted; - - struct pei_data pei_data = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .ddr3lv_support = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* enabled usb oc pin length */ - { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ - { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ - { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ - { 0, 0, 0x0000 }, /* P3: Empty */ - { 0, 0, 0x0000 }, /* P4: Empty */ - { 0, 0, 0x0000 }, /* P5: Empty */ - { 0, 0, 0x0000 }, /* P6: Empty */ - { 0, 0, 0x0000 }, /* P7: Empty */ - { 0, 4, 0x0000 }, /* P8: Empty */ - { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ - { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ - { 0, 4, 0x0000 }, /* P11: Empty */ - { 0, 4, 0x0000 }, /* P12: Empty */ - { 0, 4, 0x0000 }, /* P13: Empty */ - }, - .ddr_refresh_rate_config = 2, /* Force double refresh rate */ - }; - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (bist == 0) - enable_lapic(); - - pch_enable_lpc(); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - setup_pch_gpios(&butterfly_gpio_map); - - /* Initialize console device(s) */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected\n"); - boot_mode = 1; - - /* System is not happy after keyboard reset... */ - printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - sandybridge_early_initialization(SANDYBRIDGE_MOBILE); - printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - - boot_mode = southbridge_detect_s3_resume() ? 2 : 0; - - post_code(0x38); - /* Enable SPD ROMs and DDR-III DRAM */ - enable_smbus(); - - /* Prepare USB controller early in S3 resume */ - if (boot_mode == 2) - enable_usb_bar(); - - post_code(0x39); - - post_code(0x3a); - pei_data.boot_mode = boot_mode; - timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(&pei_data); - - timestamp_add_now(TS_AFTER_INITRAM); - post_code(0x3c); - - rcba_config(); - post_code(0x3d); - - quick_ram_check(); - post_code(0x3e); - - cbmem_was_initted = !cbmem_recovery(boot_mode==2); - if (boot_mode!=2) - save_mrc_data(&pei_data); - - if (boot_mode==2 && !cbmem_was_initted) { - /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); - } - northbridge_romstage_finalize(boot_mode==2); - - post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif - timestamp_add_now(TS_END_ROMSTAGE); +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled usb oc pin length */ + { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ + { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ + { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ + { 0, 0, 0x0000 }, /* P3: Empty */ + { 0, 0, 0x0000 }, /* P4: Empty */ + { 0, 0, 0x0000 }, /* P5: Empty */ + { 0, 0, 0x0000 }, /* P6: Empty */ + { 0, 0, 0x0000 }, /* P7: Empty */ + { 0, 4, 0x0000 }, /* P8: Empty */ + { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ + { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ + { 0, 4, 0x0000 }, /* P11: Empty */ + { 0, 4, 0x0000 }, /* P12: Empty */ + { 0, 4, 0x0000 }, /* P13: Empty */ +}; + +void mainboard_get_spd(spd_raw_data *spd) { + read_spd(&spd[0], 0x50); + read_spd(&spd[2], 0x52); }