Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35891 )
Change subject: src/southbridge/amd/pi/hudson/sata.c: set SATA in AHCI mode ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35891/1/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/sata.c:
https://review.coreboot.org/c/coreboot/+/35891/1/src/southbridge/amd/pi/huds... PS1, Line 51: /* enable AHCI mode */
ad 1) The commit deals with the south bridge, and not a specific board, doesn’t it? (The commit mess […]
ad 1) Ack. Piotr please be more verbose in the commit message, that the problem is present on apu2 and relates only to pfSense/BSD. ad 2) There is very little we can do here. Fixing closed source blob is far from possible. Assuming AGESA even doing something with SATA controller, coreboot does it in its own way in this file. So the easiest and safest option is to apply fixes here.
I understand that the commit message should be more descriptive and it caused the small confusion here.