Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.
Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81435?usp=email )
Change subject: soc/intel/xeon_sp: Move domain resources adding to their creation ......................................................................
soc/intel/xeon_sp: Move domain resources adding to their creation
Domain resources adding is moved from read_resources to domain creation so that late HOB lookup could be avoided.
TEST=intel/archercity CRB
Change-Id: Iba58dc9ac1d2e7d07004ee2bb0cc76b273d37e99 Signed-off-by: Shuo Liu shuo.liu@intel.com --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/chip_gen1.c M src/soc/intel/xeon_sp/chip_gen6.c M src/soc/intel/xeon_sp/include/soc/chip_common.h 4 files changed, 26 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/81435/1
diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index 8fc3286..6494362 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -177,9 +177,10 @@ }
void create_domain(const union xeon_domain_path dp, struct bus *upstream, - int bus_base, int bus_limit, const char *type, - struct device_operations *ops, - const size_t pci_segment_group) + int bus_base, int bus_limit, const char *type, + struct device_operations *ops, + const size_t pci_segment_group, + add_domain_resources_t add_domain_resources) { struct device_path path; init_xeon_domain_path(&path, dp.socket, dp.stack, bus_base); @@ -196,6 +197,9 @@ bus->subordinate = bus_base; bus->max_subordinate = bus_limit; bus->segment_group = pci_segment_group; + + if (add_domain_resources) + add_domain_resources(domain); }
/* Attach stack as domains */ diff --git a/src/soc/intel/xeon_sp/chip_gen1.c b/src/soc/intel/xeon_sp/chip_gen1.c index 0aa4a96..587c6ae 100644 --- a/src/soc/intel/xeon_sp/chip_gen1.c +++ b/src/soc/intel/xeon_sp/chip_gen1.c @@ -27,7 +27,7 @@ return &hob->PlatformData.IIO_resource[dn.socket].StackRes[dn.stack]; }
-static void iio_pci_domain_read_resources(struct device *dev) +static void iio_pci_domain_add_resources(struct device *dev) { struct resource *res; const STACK_RES *sr = domain_to_stack_res(dev); @@ -76,7 +76,7 @@ * all the bus numbers on the IIO stack can be used for this bridge */ static struct device_operations iio_pcie_domain_ops = { - .read_resources = iio_pci_domain_read_resources, + .read_resources = noop_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = pci_host_bridge_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) @@ -105,7 +105,7 @@ const STACK_RES *sr, const size_t pci_segment_group) { create_domain(dp, upstream, sr->BusBase, sr->BusLimit, DOMAIN_TYPE_PCIE, - &iio_pcie_domain_ops, pci_segment_group); + &iio_pcie_domain_ops, pci_segment_group, iio_pci_domain_add_resources); }
/* @@ -120,13 +120,13 @@ assert(sr->BusBase + 1 == sr->BusLimit);
create_domain(dp, upstream, sr->BusBase, sr->BusBase, DOMAIN_TYPE_UBX0, - &ubox_pcie_domain_ops, pci_segment_group); + &ubox_pcie_domain_ops, pci_segment_group, NULL); create_domain(dp, upstream, sr->BusLimit, sr->BusLimit, DOMAIN_TYPE_UBX1, - &ubox_pcie_domain_ops, pci_segment_group); + &ubox_pcie_domain_ops, pci_segment_group, NULL); }
#if CONFIG(SOC_INTEL_HAS_CXL) -static void iio_cxl_domain_read_resources(struct device *dev) +static void iio_cxl_domain_add_resources(struct device *dev) { struct resource *res; const STACK_RES *sr = domain_to_stack_res(dev); @@ -162,7 +162,7 @@ }
static struct device_operations iio_cxl_domain_ops = { - .read_resources = iio_cxl_domain_read_resources, + .read_resources = noop_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = pci_host_bridge_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) @@ -174,15 +174,18 @@
static void create_cxl_domains(const union xeon_domain_path dp, struct bus *bus, const STACK_RES *sr, const size_t pci_segment_group) + { assert(sr->BusBase + 1 <= sr->BusLimit);
/* 1st domain contains PCIe RCiEPs */ create_domain(dp, bus, sr->BusBase, sr->BusBase, DOMAIN_TYPE_PCIE, - &iio_pcie_domain_ops, pci_segment_group); + &iio_pcie_domain_ops, pci_segment_group, + iio_pci_domain_add_resources); /* 2nd domain contains CXL 1.1 end-points */ create_domain(dp, bus, sr->BusBase + 1, sr->BusLimit, DOMAIN_TYPE_CXL, - &iio_cxl_domain_ops, pci_segment_group); + &iio_cxl_domain_ops, pci_segment_group, + iio_cxl_domain_add_resources); } #endif //CONFIG(SOC_INTEL_HAS_CXL)
diff --git a/src/soc/intel/xeon_sp/chip_gen6.c b/src/soc/intel/xeon_sp/chip_gen6.c index c721685..c450f40 100644 --- a/src/soc/intel/xeon_sp/chip_gen6.c +++ b/src/soc/intel/xeon_sp/chip_gen6.c @@ -33,7 +33,7 @@ return NULL; }
-static void iio_pci_domain_read_resources(struct device *dev) +static void iio_pci_domain_add_resources(struct device *dev) { int index = 0; struct resource *res; @@ -77,7 +77,7 @@ }
static struct device_operations iio_pcie_domain_ops = { - .read_resources = iio_pci_domain_read_resources, + .read_resources = noop_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = pci_host_bridge_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) @@ -97,7 +97,8 @@ pr->BusLimit, pciroot_res_to_domain_type(sr, pr), &iio_pcie_domain_ops, - pci_segment_group); + pci_segment_group, + iio_pci_domain_add_resources); } }
diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 8acdd6d..b6c4ae0 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -59,9 +59,11 @@ void create_xeonsp_domains(const union xeon_domain_path dp, struct bus *bus, const xSTACK_RES *sr, const size_t pci_segment_group);
+typedef void (*add_domain_resources_t)(struct device *domain); void create_domain(const union xeon_domain_path dp, struct bus *upstream, int bus_base, int bus_limit, const char *type, - struct device_operations *ops, const size_t pci_segment_group); + struct device_operations *ops, const size_t pci_segment_group, + add_domain_resources_t add_domain_resources);
struct device *dev_find_device_on_socket(uint8_t socket, u16 vendor, u16 device); struct device *dev_find_all_devices_on_socket(uint8_t socket,