Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45832 )
Change subject: tgl/usb: disable TBT if hardware is not USB4 ......................................................................
tgl/usb: disable TBT if hardware is not USB4
TBT being enabled in FSP without USB4 hardware causes an issue powering off in depthcharge. Disable TBT for FSP if USB hardware is not USB4.
BUG=b:167983038 TEST=none
Change-Id: I07d5c416c79c40e9f85d721930549cf3374d327c Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/lib/fw_config.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/romstage/fsp_params.c 3 files changed, 34 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/45832/1
diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c index fdfab0a..ec32059 100644 --- a/src/lib/fw_config.c +++ b/src/lib/fw_config.c @@ -127,5 +127,5 @@ } } } -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, fw_config_init, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, fw_config_init, NULL); #endif diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 38f444b..62316c4 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -310,10 +310,15 @@ /* USB4/TBT */ for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) { dev = pcidev_on_root(SA_DEV_SLOT_TBT, i); - if (dev) + if (is_dev_enabled(dev)) { + printk(BIOS_INFO, + "ITbtPcieRootPortEn%d is enabled\n", i); params->ITbtPcieRootPortEn[i] = dev->enabled; - else + } else { + printk(BIOS_INFO, + "ITbtPcieRootPortEn%d is disabled\n", i); params->ITbtPcieRootPortEn[i] = 0; + } }
/* PCH FIVR settings override */ diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 3957299..569264c 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -14,6 +14,7 @@ #include <soc/romstage.h> #include <soc/soc_chip.h> #include <string.h> +#include <fw_config.h>
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_tigerlake_config *config) @@ -21,6 +22,7 @@ unsigned int i; uint32_t cpu_id, mask = 0; const struct device *dev; + bool usb4_device;
/* * If IGD is enabled, set IGD stolen size to 60MB. @@ -115,19 +117,40 @@ m_cfg->TcssXhciEn = config->TcssXhciEn; m_cfg->TcssXdciEn = config->TcssXdciEn;
+ usb4_device = fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) || + fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)); + /* TCSS DMA */ dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0); - m_cfg->TcssDma0En = is_dev_enabled(dev); + if (is_dev_enabled(dev) && usb4_device) { + printk(BIOS_INFO, "TcssDma0En is enabled by fw_config\n"); + m_cfg->TcssDma0En = 1; + } else { + printk(BIOS_INFO, "TcssDma0En is disabled by fw_config\n"); + m_cfg->TcssDma0En = 0; + }
dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1); m_cfg->TcssDma1En = is_dev_enabled(dev);
/* USB4/TBT */ dev = pcidev_path_on_root(SA_DEVFN_TBT0); - m_cfg->TcssItbtPcie0En = is_dev_enabled(dev); + if (is_dev_enabled(dev) && usb4_device) { + printk(BIOS_INFO, "TcssItbtPcie0En is enabled by fw_config\n"); + m_cfg->TcssItbtPcie0En = 1; + } else { + printk(BIOS_INFO, "TcssItbtPcie0En is disabled by fw_config\n"); + m_cfg->TcssItbtPcie0En = 0; + }
dev = pcidev_path_on_root(SA_DEVFN_TBT1); - m_cfg->TcssItbtPcie1En = is_dev_enabled(dev); + if (is_dev_enabled(dev) && usb4_device) { + printk(BIOS_INFO, "TcssItbtPcie1En is enabled by fw_config\n"); + m_cfg->TcssItbtPcie1En = 1; + } else { + printk(BIOS_INFO, "TcssItbtPcie1En is disabled by fw_config\n"); + m_cfg->TcssItbtPcie1En = 0; + }
dev = pcidev_path_on_root(SA_DEVFN_TBT2); m_cfg->TcssItbtPcie2En = is_dev_enabled(dev);