Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33739 )
Change subject: soc/intel/icelake: Add option to enable display over PCI external GFX ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/33739/5/src/soc/intel/icelake/romstage/fsp_p... File src/soc/intel/icelake/romstage/fsp_params.c:
https://review.coreboot.org/#/c/33739/5/src/soc/intel/icelake/romstage/fsp_p... PS5, Line 39: m_cfg->ScanExtGfxForLegacyOpRom
Why does the FSP need those settings? […]
1. The help text in Kconfig doesn't even mention the dependency to IGD. 2. Higher memory requirement also applies if IGD is enabled and an user wants to enable one or more dGPUs. 3. There's no need to dynamically adjust MMIO size in FSP. I tried to implement in coreboot, but nobody wants that feature, so it was decided to always use 2 GiB MMIO size on boards that allow the use of a dGPU. Hardcoding 2GiB should be fine and in that case we don't even need a new Kconfig for that.