Hello ron minnich, build bot (Jenkins), Philipp Hug, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36944
to look at the new patch set (#5).
Change subject: arch/riscv: Fix cpu capabilities detection function ......................................................................
arch/riscv: Fix cpu capabilities detection function
On some platforms, misa may not be implemented. On such a platform, reading misa will get 0. At this time, SOC is required to implement a non-standard function to detect the SOC's capabilities. Therefore, this modification add interfaces for non-standard function.
The MXL field of misa is always at the highest two bits, whether it is a 32-bit 64-bit or a 128-bit machine. Therefore, this modification fixes the use of a fixed offset to detect the machine length.
Change-Id: Id24f77bf21ef0c7c300faa477d67294d093eeecc Signed-off-by: Xiang Wang merle@hardenedlinux.org --- M src/arch/riscv/Makefile.inc A src/arch/riscv/cpu.c M src/arch/riscv/include/arch/cpu.h 3 files changed, 64 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/36944/5