[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/nissa/var/rull: eMMC DLL tuning

[Rui Zhou (Code Review)]

Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85933?usp=email )

Change subject: mb/google/nissa/var/rull: eMMC DLL tuning
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mb/google/nissa/var/rull: eMMC DLL tuning

According to the Intel emmc tuning results, we modify the relevant register values
recommended in b:386317255/comment16 to ensure good emmc performance.

BUG=b:386317255
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: Ibdbb96f9623612a8eb5e01818859c4844ca4de13
Signed-off-by: Rui Zhou 
---
M src/mainboard/google/brya/variants/rull/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/85933/1

diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb
index 6e7c2c2..e1d94f9 100644
--- a/src/mainboard/google/brya/variants/rull/overridetree.cb
+++ b/src/mainboard/google/brya/variants/rull/overridetree.cb
@@ -58,7 +58,7 @@
    #         11: Reserved
    # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
    # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
-	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004C"
+	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023"

# EMMC Rx Strobe Delay
    # Refer to EDS-Vol2-42.3.11.