[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: add MaxDramSpeed config

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57866 )

Change subject: soc/intel/alderlake: add MaxDramSpeed config
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soc/intel/alderlake: add MaxDramSpeed config

This change add MaxDramSpeed for variants usage to config dram speed.

Signed-off-by: Casper Chang 
Change-Id: Iba0fae0ab4ff0121dc63af792458492eeb21ec2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57866
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 4 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 5f556c8..b9be02b 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -436,6 +436,8 @@
    * 0 = VR_DOMAIN_IA Core 1 = VR_DOMAIN_GT.
    */
    struct vr_config domain_vr_config[NUM_VR_DOMAINS];
+
+	uint16_t MaxDramSpeed;
 };

typedef struct soc_intel_alderlake_config config_t;
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 2d0f6da..698cff6 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -136,6 +136,8 @@
 {
    m_cfg->SaGv = config->SaGv;
    m_cfg->RMT = config->RMT;
+	if (config->MaxDramSpeed)
+		m_cfg->DdrFreqLimit = config->MaxDramSpeed;
 }

static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,