[coreboot-gerrit] Change in coreboot[master]: riscv: simplify timer interrupt handling

[Philipp Hug (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/29340

to look at the new patch set (#4).

Change subject: riscv: simplify timer interrupt handling
......................................................................

riscv: simplify timer interrupt handling

Just disable the timer interrupt and notify supervisor.
To receive another timer interrupt just set timecmp and
enable machine mode timer interrupt again.

TEST=Run linux on sifive unleashed

Change-Id: I5d693f872bd492c9d0017b514882a4cebd5ccadd
Signed-off-by: Philipp Hug 
---
M src/arch/riscv/trap_handler.c
1 file changed, 8 insertions(+), 51 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29340/4