[coreboot-gerrit] [S] Change in coreboot[master]: mb/starlabs/starbook: Disable ASPM in coreboot

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73982 )

Change subject: mb/starlabs/starbook: Disable ASPM in coreboot
......................................................................

mb/starlabs/starbook: Disable ASPM in coreboot

ASPM is already configured by FSP so disable it in coreboot to
reduce boot time by a whopping 34ms.

Signed-off-by: Sean Rhodes 
Change-Id: I073c68dafa9baa90e253b5230f84b0de6a7e5c47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73982
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
Reviewed-by: Jakub Czapiga 
---
M src/mainboard/starlabs/starbook/Kconfig
1 file changed, 38 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, but someone else must approve
  Jakub Czapiga: Looks good to me, approved

diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig
index d35a4d2..b2dfe12 100644
--- a/src/mainboard/starlabs/starbook/Kconfig
+++ b/src/mainboard/starlabs/starbook/Kconfig
@@ -145,9 +145,30 @@
    string
    default "3rdparty/blobs/mainboard/starlabs/Logo.bmp"

+config PCIEXP_ASPM
+	bool
+	default n
+	help
+	  FSP is already taking care of ASPM, which is configured through the devicetree in coreboot
+	  on Alderlake Platforms. Disable it to save some boot time.
+
 config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS
    default 32

+config PCIEXP_L1_SUB_STATE
+	bool
+	default n
+	help
+	  Enabling PCIe L1 sub states is already done in FSP.
+	  Disable it to save some boot time.
+
+config PCIEXP_CLK_PM
+	bool
+	default n
+	help
+	  Enabling PCIe clock power management is already done in FSP.
+	  Disable it to save some boot time
+
 config SOC_INTEL_CSE_SEND_EOP_EARLY
    default n if BOARD_STARLABS_STARBOOK_ADL