[coreboot-gerrit] Change in coreboot[master]: soc/intel/broadwell: Add ECC config reporting

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46367 )

Change subject: soc/intel/broadwell: Add ECC config reporting
......................................................................

soc/intel/broadwell: Add ECC config reporting

This has been taken from Haswell, and is just to reduce differences.

Change-Id: Ib872cbcd20d6e212b1f55400aa350dc6ba44dc2a
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46367
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/soc/intel/broadwell/romstage/raminit.c
1 file changed, 8 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index 65e386a..7020ddf 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -21,6 +21,13 @@
 #include <soc/romstage.h>
 #include <soc/systemagent.h>

+static const char *const ecc_decoder[] = {
+	"inactive",
+	"active on IO",
+	"disabled on IO",
+	"active",
+};
+
 /*
  * Dump in the log memory controller configuration as read from the memory
  * controller registers.
@@ -43,7 +50,7 @@
    	const u32 ch_conf = MCHBAR32(MAD_DIMM(i));

printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
-
+		printk(BIOS_DEBUG, "   ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
    	printk(BIOS_DEBUG, "   enhanced interleave mode %s\n",
    	       ((ch_conf >> 22) & 1) ? "on" : "off");