Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Elyes Haouas, Tim Chu.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69065 )
Change subject: /: Fix 16-bit read/write PCI_COMMAND register ......................................................................
Patch Set 1: Code-Review-1
(4 comments)
Patchset:
PS1: What does this exactly fix? Do you if all of these are actually wrong or intended?
File src/drivers/usb/pci_ehci.c:
https://review.coreboot.org/c/coreboot/+/69065/comment/9ae67cec_924a2a23 PS1, Line 53: pci_s_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | : PCI_COMMAND_MASTER); Do you know if it might be intended to leave the upper bits untouched?
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/69065/comment/9cf04606_618b88b2 PS1, Line 985: pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); Do you know if clearing the status registers bit was intended or not here?
File src/southbridge/amd/cimx/sb800/late.c:
https://review.coreboot.org/c/coreboot/+/69065/comment/e01a5975_649de745 PS1, Line 100: dev->command |= PCI_COMMAND_MASTER; : pci_write_config8(dev, PCI_COMMAND, dev->command); Do you know if skip setting the upper 8bit is intended?