Hello Rizwan Qureshi,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/37282
to review the following change.
Change subject: soc/intel/common/block/cse: Rename set_host_ready() to cse_set_host_ready() ......................................................................
soc/intel/common/block/cse: Rename set_host_ready() to cse_set_host_ready()
Below changes are done: 1. Rename set_host_ready() function to cse_set_host_ready() 2. Additional debug messages are added
TEST=Build and Boot hatch board.
Change-Id: Icfcf1631cc37faacdea9ad84be55f5710104bad5 Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 7 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/37282/1
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index f81411a..46ad8ce 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -272,7 +272,7 @@ }
/* Makes the host ready to communicate with CSE */ -void set_host_ready(void) +void cse_set_host_ready(void) { uint32_t csr; csr = read_host_csr(); @@ -286,10 +286,13 @@ { struct stopwatch sw; stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY); + printk(BIOS_ERR, "HECI: Wait 15 secs for CSE to enter SEC_OVERRIDE mode!\n"); while (!check_cse_sec_override_mode()) { udelay(HECI_DELAY); - if (stopwatch_expired(&sw)) + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "HECI: Timed out!\n"); return 0; + } }
return 1; @@ -545,7 +548,7 @@
if (wait_heci_ready()) { /* Device is back on its imaginary feet, clear reset */ - set_host_ready(); + cse_set_host_ready(); return 1; }
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 4c00006..3c00b87 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -112,7 +112,7 @@
/* Makes the host ready to communicate with CSE*/ -void set_host_ready(void); +void cse_set_host_ready(void);
/* * Polls for ME state 'HECI_OP_MODE_SEC_OVERRIDE' for 15 seconds.