[coreboot-gerrit] Change in coreboot[master]: intel/i440bx: Resolve long standing raminit TODOs

[Keith Hui (Code Review)]

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38383 )

Change subject: intel/i440bx: Resolve long standing raminit TODOs
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intel/i440bx: Resolve long standing raminit TODOs

Drop DRAMT write as it's only rewriting the power on default.

PMCR write is required. Update comment on its purpose and move to
end of sdram_enable().

Change-Id: I62e8b2531f0f297ffb7db440db89ffa65771b7d5
Signed-off-by: Keith Hui 
---
M src/northbridge/intel/i440bx/raminit.c
1 file changed, 3 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/38383/1

diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index d5c23cf..5ce5e5b 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -985,13 +985,6 @@

/* Setup DRAM buffer strength. */
    set_dram_buffer_strength();
-
-	/* TODO: Set PMCR? */
-	// pci_write_config8(NB, PMCR, 0x14);
-	pci_write_config8(NB, PMCR, 0x10);
-
-	/* TODO: This is for EDO memory only. */
-	pci_write_config8(NB, DRAMT, 0x03);
 }

static void sdram_enable(void)
@@ -1034,6 +1027,9 @@
    spd_enable_refresh();
    udelay(1);

+	/* Enable normal refresh with the NB. */
+	pci_write_config8(NB, PMCR, 0x10);
+
    PRINT_DEBUG("Northbridge following SDRAM init:\n");
    DUMPNORTH();
 }