Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48080 )
Change subject: mainboard/intel/adlrvp: Enable PCH PCIe device over x1 slot ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48080/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48080/4//COMMIT_MSG@12 PS4, Line 12: Drive OEB 7:GPP_A7 and OEB 6:GPP_E5 low
Added W/A in commit msg, hope that is okay
SG. Thanks!
https://review.coreboot.org/c/coreboot/+/48080/4/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48080/4/src/mainboard/intel/adlrvp/... PS4, Line 54: free running CLK
you mean PcieClkSrcUsage[6]="7" ? because CLK6 is for RP6 already. […]
Why is that? Don't mean to block this change, but I am interested in understanding why the normal configuration as stated above does not work. Is there a hardware bug? Or any other limitation you are aware of?