Duan huayang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40525 )
Change subject: soc/mediatek/mt8183: Set CA and DQ vref range to correct value ......................................................................
Patch Set 11:
(3 comments)
https://review.coreboot.org/c/coreboot/+/40525/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40525/8//COMMIT_MSG@11 PS8, Line 11: .
Hi huayang, this is not Done - please add that reference to your commit message. Something like: […]
Done
https://review.coreboot.org/c/coreboot/+/40525/9/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/40525/9/src/soc/mediatek/mt8183/dra... PS9, Line 1378: * dramc init using dramc_setting_DDRxxx() to overwrite the default settings.
Second part of the string is not done: […]
Done
https://review.coreboot.org/c/coreboot/+/40525/7/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/40525/7/src/soc/mediatek/mt8183/dra... PS7, Line 272: if (fsp == FSP_0) { : mr->MR13Value &= ~(1 << 6); : mr->MR13Value &= 0x7f; : } else { : mr->MR13Value |= (1 << 6); : mr->MR13Value |= 0x80; : }
The update of MR13 only depends on freq_group, which is always the same in each call to dramc_cmd_bu […]
yes, you are right, MR13 have been set to correct value at dramc_mode_reg_init(), so not update it again at command bus training.