Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39625 )
Change subject: soc/intel/xeon_sp: Modify FSP-T code caching parameters ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39625/1/src/soc/intel/xeon_sp/bootb... File src/soc/intel/xeon_sp/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/39625/1/src/soc/intel/xeon_sp/bootb... PS1, Line 33: .CodeRegionBase = (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE), : .CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE, The value we need here has nothing to do with CBFS. What you want to get here is size of BIOS IFD region, which is 16MB on TiogaPass. As the last resort, please rename this config variable to BIOS_REGION_SIZE and have it defined by mainboard code.
However, there may be a better alternative. Could you please try the following change and let me know if this works: 1. set CodeRegionBase to 0 2. set CodeRegionLength to 0
and then see if this resolves the booting issue.
This works on next generation platform well, and the caching is re-enabled when fast_spi_cache_bios_region() is called, right after FSP-T exit.