[coreboot-gerrit] Change in coreboot[master]: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg

[Sridhar Siricilla (Code Review)]

Hello Rizwan Qureshi,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/35227

to review the following change.

Change subject: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg
......................................................................

src/soc/intel/common/block/cse: Add funtion to send CSE reset msg

Add send_heci_reset_req_message() to send reset request to CSE. This
reset can be GLOBAL RESET/HOST ONLY RESET/CSE ONLY RESET.

Change-Id: I29b560dde1549b8268163e18d9b1bbbf1935d54a
Signed-off-by: sridhar 
Signed-off-by: Rizwan Qureshi 
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 70 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35227/1

diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 7697a4a..9585a09 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -69,10 +69,18 @@

#define HECI_OP_MODE_SEC_OVERRIDE 5

+/* Global Reset Command ID */
+#define MKHI_GLOBAL_RESET_REQ	0xb
+#define MKHI_GROUP_ID_CBM	0
+
+/* RST Origin */
+#define GR_ORIGIN_BIOS_POST	2
+
 static struct cse_device {
    uintptr_t sec_bar;
 } g_cse;

+/* HFSTS1 */
 union me_hfs {
         u32 data;
         struct {
@@ -595,6 +603,54 @@
    return reg;
 }

+/*
+ * Sends GLOBAL_RESET_REQ cmd to CSE.The reset can be GLOBAL_RESET/
+ * HOST_RESET_ONLY/HOST_RESET_ONLY.
+ */
+int send_heci_reset_req_message(u8 rst_type)
+{
+       int status;
+       struct reset_reply {
+               u8 group_id;
+               u8 command;
+               u8 reserved;
+               u8 result;
+       } __packed reply;
+       struct reset_message {
+               u8 group_id;
+               u8 cmd;
+               u8 reserved;
+               u8 result;
+               u8 req_origin;
+               u8 reset_type;
+       } __packed;
+       struct reset_message msg = {
+              .group_id = MKHI_GROUP_ID_CBM,
+               .cmd = MKHI_GLOBAL_RESET_REQ,
+               .req_origin = GR_ORIGIN_BIOS_POST,
+               .reset_type = rst_type
+       };
+       size_t reply_size;
+
+       if (!((rst_type == GLOBAL_RESET)
+		|| (rst_type == HOST_RESET_ONLY)
+		|| (rst_type == CSE_RESET_ONLY))) {
+	       return -1;
+       }
+
+       heci_reset();
+
+       reply_size = sizeof(reply);
+       memset(&reply, 0, reply_size);
+
+       printk(BIOS_ERR, "HECI Global Reset(type=%d) Command\n", rst_type);
+       status = heci_send_receive(&msg, sizeof(msg), &reply, &reply_size);
+       if (status != 1)
+              return -1;
+
+       printk(BIOS_DEBUG, "HECI GBL RST success!\n");
+       return 0;
+}

#if ENV_RAMSTAGE

diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index 82e07cf..ceeca88e 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -70,6 +70,13 @@
  */
 int wait_cse_rec(void);

+/*
+ * Sends GLOBAL_RESET_REQ cmd to CSE.The reset can be
+ * GLOBAL_RESET/HOST_RESET_ONLY/HOST_RESET_ONLY.
+ * Returns -1 on failure a 0 on success.
+ */
+int send_heci_reset_req_message(u8 rst_type);
+
 #define BIOS_HOST_ADDR							0x00
 #define HECI_MKHI_ADDR							0x07

@@ -83,4 +90,11 @@
         PCI_ME_HFSTS6 = 0x6C,
 };

+
+/* Command GLOBAL_RESET_REQ Reset Types */
+#define GLOBAL_RESET       1
+#define HOST_RESET_ONLY    2
+#define CSE_RESET_ONLY     3
+
+
 #endif // SOC_INTEL_COMMON_MSR_H