Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57051 )
Change subject: soc/amd/common/block/lpc,mb/google/guybrush: Use #defines for eSPI setup ......................................................................
soc/amd/common/block/lpc,mb/google/guybrush: Use #defines for eSPI setup
It's hard to understand what this code is doing because it uses hard coded values. Most of these are public so use #defines instead.
BUG=none TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: I2d74ed3b9b4984ab1e2a22c50375baf9c9589df0 --- M src/mainboard/google/guybrush/bootblock.c M src/soc/amd/common/block/include/amdblocks/lpc.h 2 files changed, 14 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/57051/1
diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index dc5e046..550dee4 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -2,12 +2,14 @@
#include <amdblocks/acpimmio.h> #include <amdblocks/espi.h> +#include <amdblocks/lpc.h> #include <bootblock_common.h> #include <baseboard/variants.h> #include <console/console.h> #include <delay.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> +#include <soc/southbridge.h> #include <timer.h>
#define FC350_PCIE_INIT_DELAY_US (20 * USECS_PER_MSEC) @@ -46,20 +48,21 @@
printk(BIOS_DEBUG, "Bootblock configure eSPI\n");
- dword = pci_read_config32(SOC_LPC_DEV, 0x78); - dword &= 0xFFFFF9F3; - dword |= 0x200; - pci_write_config32(SOC_LPC_DEV, 0x78, dword); - pci_write_config32(SOC_LPC_DEV, 0x44, 0); - pci_write_config32(SOC_LPC_DEV, 0x48, 0); + dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS); + dword &= ~(LDRQ0_PD_EN | LDRQ0_EN | BIT(3)); + dword |= LDRQ0_PU_EN; + pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword); + + pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, 0); + pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, 0);
dword = pm_read32(0x90); dword |= 1 << 16; pm_write32(0x90, dword);
- dword = pm_read32(0x74); + dword = pm_read32(PM_ACPI_CONF); dword |= 3 << 10; - pm_write32(0x74, dword); + pm_write32(PM_ACPI_CONF, dword); }
void bootblock_mainboard_init(void) diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index aa483e4..0bc171a 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -105,6 +105,9 @@ #define LPC_ALT_WIDEIO0_ENABLE BIT(0)
#define LPC_MISC_CONTROL_BITS 0x78 +#define LDRQ0_PD_EN BIT(10) +#define LDRQ0_PU_EN BIT(9) +#define LDRQ0_EN BIT(2) #define LPC_NOHOG BIT(0)
#define LPC_TRUSTED_PLATFORM_MODULE 0x7c