Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34449 )
Change subject: soc/intel/common: Set controller state to active in GSPI init ......................................................................
soc/intel/common: Set controller state to active in GSPI init
Set the controller state to D0 during the GSPI sequence, this ensures the controller is up and active.
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I2f95059453ca5565a38650b147590ece4d8bf5ed --- M src/soc/intel/common/block/gspi/gspi.c 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/34449/1
diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 17532bf..8bcefe2 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -24,6 +24,7 @@ #include <intelblocks/chip.h> #include <intelblocks/gspi.h> #include <intelblocks/spi.h> +#include <intelblocks/lpss.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <string.h> @@ -151,6 +152,7 @@ const struct gspi_cfg *cfg = gspi_get_cfg(); int devfn; uintptr_t gspi_base_addr; + const struct device *tree_dev;
assert(gspi_max != 0); if (!cfg) { @@ -172,6 +174,9 @@ devfn = gspi_soc_bus_to_devfn(gspi_bus); gspi_set_base_addr(devfn, NULL, GSPI_BUS_BASE(gspi_base_addr, gspi_bus)); + tree_dev = pcidev_path_on_root(devfn); + /* Ensure controller is in D0 state */ + lpss_set_power_state(tree_dev, STATE_D0); } }
@@ -449,6 +454,9 @@ uint32_t cs_ctrl, sscr0, sscr1, clocks, sitf, sirf, pol; struct gspi_ctrlr_params params, *p = ¶ms;
+ /* Ensure controller is in D0 state */ + lpss_set_power_state((struct device*) dev, STATE_D0); + /* Only chip select 0 is supported. */ if (dev->cs != 0) { printk(BIOS_ERR, "%s: Invalid CS value: cs=%u.\n", __func__,