Hello Subrata Banik,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/29752
to review the following change.
Change subject: mb/google/dragonegg: Enable trackpad ......................................................................
mb/google/dragonegg: Enable trackpad
BUG=b:112282079 BRANCH=None TEST=1. run evtest and make sure trackpad shows up in list 2. Able to wake system from S3 using trackpad
Change-Id: I86d6b7815147d558065611604363bb607119c154 Signed-off-by: Shelley Chen shchen@google.com Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb M src/mainboard/google/dragonegg/variants/baseboard/gpio.c 2 files changed, 13 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29752/1
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb index da7ee5a..b494ac9 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb @@ -227,7 +227,15 @@ end device pci 14.5 on end # SDCard device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D1_IRQ)" + register "wake" = "GPE0_DW1_00" + device i2c 15 on end + end + end # I2C #1 device pci 15.2 on end # I2C #2 device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 diff --git a/src/mainboard/google/dragonegg/variants/baseboard/gpio.c b/src/mainboard/google/dragonegg/variants/baseboard/gpio.c index 6e0928f..acb3171 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/gpio.c +++ b/src/mainboard/google/dragonegg/variants/baseboard/gpio.c @@ -37,6 +37,10 @@ /* HP_INT_L */ PAD_CFG_GPI(GPP_C15, NONE, PLTRST), /* PCH_DEV_INT_ODL */ PAD_CFG_GPI(GPP_C22, NONE, PLTRST), /* PCH_DEV_RESET_L */ PAD_CFG_GPO(GPP_C23, 0, PLTRST), +/* TRACKPAD_WAKE */ PAD_CFG_GPI_SCI(GPP_D0, NONE, DEEP, EDGE_SINGLE, + INVERT), +/* TRACKPAD_INT_ODL */ PAD_CFG_GPI_APIC(GPP_D1, NONE, DEEP, EDGE_SINGLE, + INVERT), /* PCI_NVME_CLKREQ_ODL */ PAD_CFG_NF(GPP_D7, UP_20K, PWROK, NF1), /* H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_D16, UP_20K, PLTRST, LEVEL, INVERT),