[coreboot-gerrit] Change in coreboot[master]: security/intel/txt: Improve MTRR setup for GETSEC[ENTERACCS]

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44880 )

Change subject: security/intel/txt: Improve MTRR setup for GETSEC[ENTERACCS]
......................................................................

Patch Set 15:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44880/15/src/security/intel/txt/get... 
File src/security/intel/txt/getsec_enteraccs.S:

https://review.coreboot.org/c/coreboot/+/44880/15/src/security/intel/txt/get... 
PS15, Line 111: Disable all MTRRs
> FYI that on DeltaLake, coreboot sets default memory attribute as WB instead of UC, through MSR 0x2ff.

Right. This code modifies the default memory attribute without restoring it. This is fixed in https://review.coreboot.org/c/coreboot/+/46375 (now merged)