[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Modify FSP-T code caching parameters

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39625 )

Change subject: soc/intel/xeon_sp: Modify FSP-T code caching parameters
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Patch Set 3:

We have CACHE_ROM_BASE/_SIZE (cpu/x86/mtrr.h) for such occasions. It's
based on CONFIG_ROM_SIZE but I don't see how that would matter? We might
mark a little too much as cacheable, but does it hurt if we never access
those addresses?