[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake/bootblock: Clear the GPI IS & IE registers

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34624 )

Change subject: soc/intel/cannonlake/bootblock: Clear the GPI IS & IE registers
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Patch Set 3:

what is the real problem statement here?

GPI Interrupt Enable (GPI_INT_EN_GPPC_A_0): This bit is
used to enable/disable the generation of APIC interrupt when the
corresponding GPI_INT_STS bit is set.
0 = disable interrupt generation
1 = enable interrupt generation

i don't think if this bit remain set alone won't cause any issue unless GPI_INT_STS bit is also set at that time?