[coreboot-gerrit] New patch to review for coreboot: 4ae6a7e usbdebug: Change reference to EHCI BAR

[Kyösti Mälkki]

Kyösti Mälkki ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3875

-gerrit

commit 4ae6a7e8ef88048f283e579c65991a86c6bf099a
Author: Kyösti Mälkki 
Date:   Fri Aug 16 06:34:04 2013 +0300

usbdebug: Change reference to EHCI BAR

Change the defines, as follow-up patch will replace use of
    constant CONFIG_EHCI_BAR.

Change-Id: I44ff77cb7a2826f3b43d8d46440fd4482a29d18c
    Signed-off-by: Kyösti Mälkki 
---
 src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 9 +++++----
 src/southbridge/amd/sb700/enable_usbdebug.c        | 9 +++++----
 src/southbridge/amd/sb800/enable_usbdebug.c        | 9 +++++----
 3 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
index bd62842..6fa1781 100644
--- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
@@ -30,19 +30,20 @@
 #define HUDSON_DEVN_BASE 0
 #endif

-#define EHCI_EOR		(CONFIG_EHCI_BAR + 0x20)
-#define DEBUGPORT_MISC_CONTROL	(EHCI_EOR + 0x80)
+#define EHCI_EOR				0x20
+#define DEBUGPORT_MISC_CONTROL		0x80

void set_debug_port(unsigned int port)
 {
+	u32 base_regs = CONFIG_EHCI_BAR + EHCI_EOR;
    u32 reg32;

/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
-	reg32 = read32(DEBUGPORT_MISC_CONTROL);
+	reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL);
    reg32 &= ~(0xf << 28);
    reg32 |= (port << 28);
    reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
-	write32(DEBUGPORT_MISC_CONTROL, reg32);
+	write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
 }

diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c
index 6c46071..0712d2a 100644
--- a/src/southbridge/amd/sb700/enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/enable_usbdebug.c
@@ -27,19 +27,20 @@
 #include <device/pci_def.h>
 #include "sb700.h"

-#define EHCI_EOR		(CONFIG_EHCI_BAR + 0x20)
-#define DEBUGPORT_MISC_CONTROL	(EHCI_EOR + 0x80)
+#define EHCI_EOR				0x20
+#define DEBUGPORT_MISC_CONTROL		0x80

void set_debug_port(unsigned int port)
 {
+	u32 base_regs = CONFIG_EHCI_BAR + EHCI_EOR;
    u32 reg32;

/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
-	reg32 = read32(DEBUGPORT_MISC_CONTROL);
+	reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL);
    reg32 &= ~(0xf << 28);
    reg32 |= (port << 28);
    reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
-	write32(DEBUGPORT_MISC_CONTROL, reg32);
+	write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
 }

/*
diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c
index d17e955..6422fa2 100644
--- a/src/southbridge/amd/sb800/enable_usbdebug.c
+++ b/src/southbridge/amd/sb800/enable_usbdebug.c
@@ -30,19 +30,20 @@
 #define SB800_DEVN_BASE 0
 #endif

-#define EHCI_EOR		(CONFIG_EHCI_BAR + 0x20)
-#define DEBUGPORT_MISC_CONTROL	(EHCI_EOR + 0x80)
+#define EHCI_EOR				0x20
+#define DEBUGPORT_MISC_CONTROL		0x80

void set_debug_port(unsigned int port)
 {
+	u32 base_regs = CONFIG_EHCI_BAR + EHCI_EOR;
    u32 reg32;

/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
-	reg32 = read32(DEBUGPORT_MISC_CONTROL);
+	reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL);
    reg32 &= ~(0xf << 28);
    reg32 |= (port << 28);
    reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
-	write32(DEBUGPORT_MISC_CONTROL, reg32);
+	write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
 }