[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode

[build bot (Jenkins) (Code Review)]

Attention is currently required from: Tarun Tuli, Subrata Banik, Bora Guvendik.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70165 )

Change subject: soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode
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Patch Set 1:

(1 comment)

Commit Message:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164877):
https://review.coreboot.org/c/coreboot/+/70165/comment/f7a272a1_2b843da8 
PS1, Line 10: continous clock output.
'continous' may be misspelled - perhaps 'continuous'?