Aaron Durbin (adurbin@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4880
-gerrit
commit 55c54e62ef4db04933f67038457be97b157c141c Author: Aaron Durbin adurbin@chromium.org Date: Thu Oct 10 21:03:50 2013 -0500
baytrail: add vboot ramstage verification
Add suport for verifying the ramstage with vboot during romstage execution. Along with this support select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to cache the relocated ramstage 1MiB below the top end of the TSEG region.
BUG=chrome-os-partner:23249 BRANCH=None TEST=Built and booted with CONFIG_VBOOT_VERIFY_FIRMWARE=y selected.
Signed-off-by: Aaron Durbin adurbin@chromium.org Change-Id: I355f62469bdcca62b0a4468100effab0342dc8fc Reviewed-on: https://chromium-review.googlesource.com/172712 Reviewed-by: Shawn Nematbakhsh shawnn@chromium.org --- src/soc/intel/baytrail/romstage/romstage.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 4228615..4d74b53 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -25,12 +25,15 @@ #include <console/console.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> +#include <ramstage_cache.h> #include <romstage_handoff.h> #include <timestamp.h> +#include <vendorcode/google/chromeos/chromeos.h> #include <baytrail/gpio.h> #include <baytrail/iomap.h> #include <baytrail/lpc.h> #include <baytrail/pci_devs.h> +#include <baytrail/reset.h> #include <baytrail/romstage.h>
static inline uint64_t timestamp_get(void) @@ -169,6 +172,9 @@ void asmlinkage romstage_after_car(void)
timestamp_add_now(TS_END_ROMSTAGE);
+ /* Run vboot verification if configured. */ + vboot_verify_firmware(romstage_handoff_find_or_add()); + /* Load the ramstage. */ copy_and_run(); while (1); @@ -270,3 +276,25 @@ static void *setup_stack_and_mttrs(void)
return slot; } + +struct ramstage_cache *ramstage_cache_location(long *size) +{ + char *smm_base; + /* 1MiB cache size */ + const long cache_size = (1 << 20); + + /* Ramstage cache lives in TSEG region which is the definition of + * cbmem_top(). */ + smm_base = cbmem_top(); + *size = cache_size; + return (void *)&smm_base[CONFIG_SMM_TSEG_SIZE - cache_size]; +} + +void ramstage_cache_invalid(struct ramstage_cache *cache) +{ +#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE + /* Perform cold reset on invalid ramstage cache. */ + cold_reset(); +#endif +} +