Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32542
Change subject: mb/siemens/mc_apl2: Limit SD-Card speed to DDR50 ......................................................................
mb/siemens/mc_apl2: Limit SD-Card speed to DDR50
Due to PCB limitations the SD-Card interface is not able to operate with the highest frequency reliably. The OS driver will switch to the highest mode if a SD-Card is attached which supports this high frequency mode. In order to work around this PCB limitation disable the high frequency modes in the controller capabilities (SDR104 and HS400 mode) and leave SDR50 and DDR50 enabled.
Change-Id: Ia5fed5fb70b027de34170b49620927614a00fb7a Signed-off-by: Werner Zeh werner.zeh@siemens.com --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c 1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32542/1
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c index 0c2418a..1cbb689 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c @@ -23,11 +23,17 @@ #include <timer.h> #include <timestamp.h> #include <baseboard/variants.h> +#include <soc/pci_devs.h> + +#define SD_CAP_BYP 0x810 +#define SD_CAP_BYP_EN 0x5A +#define SD_CAP_BYP_REG1 0x814
void variant_mainboard_final(void) { struct device *dev; uint16_t cmd = 0; + void *base;
/* Set Master Enable for on-board PCI device. */ dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); @@ -36,6 +42,22 @@ cmd |= PCI_COMMAND_MASTER; pci_write_config16(dev, PCI_COMMAND, cmd); } + + /* Reduce SD-Card speed to DDR50 because of PCB constraints. */ + dev = dev_find_slot(0, PCH_DEVFN_SDCARD); + if (dev) { + uint32_t reg; + base = (void *)(pci_read_config32(dev, PCI_BASE_ADDRESS_0) & + ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); + if (!base) + return; + + write32(base + SD_CAP_BYP, SD_CAP_BYP_EN); + reg = read32(base + SD_CAP_BYP_REG1); + /* Disable HS400 and SDR104, keep SDR50 and DDR50 modes. */ + reg &= ~0x20005800; + write32(base + SD_CAP_BYP_REG1, reg); + } }
static void wait_for_legacy_dev(void *unused)