Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30728
Change subject: southbridge/amd/cimx: Drop unused functions ......................................................................
southbridge/amd/cimx: Drop unused functions
Leftovers from attempts of using these with native (non-AGESA) amdfam10/15 support code.
Change-Id: I8eaed338438e1de5baee462376e339e1439f72f1 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/southbridge/amd/cimx/sb800/early.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/cimx/sb800/sb_cimx.h M src/southbridge/amd/cimx/sb900/early.c M src/southbridge/amd/cimx/sb900/sb_cimx.h 5 files changed, 0 insertions(+), 65 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/30728/1
diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 3e2c10a..adc69d8 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -22,25 +22,6 @@ #include "cbmem.h"
/** - * @brief Get SouthBridge device number - * @param[in] bus target bus number - * @return southbridge device number - */ -u32 get_sbdn(u32 bus) -{ - pci_devfn_t dev; - - printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__); - //dev = PCI_DEV(bus, 0x14, 0); - dev = pci_locate_device_on_bus( - PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_SM), - bus); - - printk(BIOS_DEBUG, "SB800 - %s - %s - End.\n", __FILE__, __func__); - return (dev >> 15) & 0x1f; -} - -/** * @brief South Bridge CIMx romstage entry, * wrapper of sbPowerOnInit entry point. */ diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index e3390d5..c66206f 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -364,22 +364,8 @@
case PCI_DEVFN(0x14, 0): /* 0:14:0 SMBUS */ clear_ioapic(VIO_APIC_VADDR); -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA) /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); -#else - /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ -#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) - /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ - setup_ioapic(VIO_APIC_VADDR, - CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); -#elif (CONFIG_APIC_ID_OFFSET > 0) - /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ - setup_ioapic(VIO_APIC_VADDR, 0); -#else -#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" -#endif -#endif break;
case PCI_DEVFN(0x14, 1): /* 0:14:1 IDE */ diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h index 16ac6fe..6c924ca 100644 --- a/src/southbridge/amd/cimx/sb800/sb_cimx.h +++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h @@ -34,10 +34,4 @@ */ void sb800_clk_output_48Mhz(void);
-/** - * @brief Get SouthBridge device number, called by finalize_node_setup() - * @param[in] bus target bus number - * @return southbridge device number - */ -u32 get_sbdn(u32 bus); #endif diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index 96f5e33..6fe133b 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -25,25 +25,6 @@ #include <commonlib/loglevel.h> #include "smbus.h"
-/** - * @brief Get SouthBridge device number - * @param[in] bus target bus number - * @return southbridge device number - */ -u32 get_sbdn(u32 bus) -{ - pci_devfn_t dev; - - printk(BIOS_SPEW, "SB900 - Early.c - get_sbdn - Start.\n"); - - dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_SB900_SM), bus); - - printk(BIOS_SPEW, "SB900 - Early.c - get_sbdn - End.\n"); - - return (dev >> 15) & 0x1f; -} -
/** * @brief South Bridge CIMx romstage entry, diff --git a/src/southbridge/amd/cimx/sb900/sb_cimx.h b/src/southbridge/amd/cimx/sb900/sb_cimx.h index 99b246e..d13c79d 100644 --- a/src/southbridge/amd/cimx/sb900/sb_cimx.h +++ b/src/southbridge/amd/cimx/sb900/sb_cimx.h @@ -33,13 +33,6 @@ #define REV_SB900_A12 0x12
/** - * @brief Get SouthBridge device number, called by finalize_node_setup() - * @param[in] bus target bus number - * @return southbridge device number - */ -u32 get_sbdn(u32 bus); - -/** * South Bridge CIMx romstage entry, sbPowerOnInit entry point wrapper. */ void sb_poweron_init(void);