[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Clear the GPI IS & IE registers

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34624 )

Change subject: soc/intel/cannonlake: Clear the GPI IS & IE registers
......................................................................

Patch Set 4:
> Patch Set 3:
> > Patch Set 3:
> > > Patch Set 3:
> > >
> > > what is the real problem statement here?
> > >
> > > GPI Interrupt Enable (GPI_INT_EN_GPPC_A_0): This bit is
> > > used to enable/disable the generation of APIC interrupt when the
> > > corresponding GPI_INT_STS bit is set.
> > > 0 = disable interrupt generation
> > > 1 = enable interrupt generation
> > >
> > > i don't think if this bit remain set alone won't cause any issue unless GPI_INT_STS bit is also set at that time?
> >
> > Only when the system enters G3, these registers are reset. In other states, they are not reset. This becomes more of a problem when one SKU of a variant uses the concerned GPIO and a different SKU of the same variant does not use the concerned GPIO. For more context please refer to b/130593883.
>
> Thanks for the pointer, what is the PAD reset configuration for that GPIO PIN ? (where you are seeing its only resetting in G3)

Looks like i don't have access b/130593883