[coreboot-gerrit] Change in ...coreboot[master]: northbridge: Remove unused include <device/pci_ops.h>

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33529

Change subject: northbridge: Remove unused include <device/pci_ops.h>
......................................................................

northbridge: Remove unused include <device/pci_ops.h>

Change-Id: Ib60305948ac1d3464586fe69501bd28eecb761ee
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/amd/pi/00730F01/iommu.c
M src/northbridge/intel/gm45/bootblock.c
M src/northbridge/intel/haswell/bootblock.c
M src/northbridge/intel/i945/bootblock.c
M src/northbridge/intel/nehalem/bootblock.c
M src/northbridge/intel/nehalem/finalize.c
M src/northbridge/intel/pineview/bootblock.c
M src/northbridge/intel/sandybridge/bootblock.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/bootblock.c
M src/northbridge/via/vx900/bootblock.c
11 files changed, 0 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/33529/1

diff --git a/src/northbridge/amd/pi/00730F01/iommu.c b/src/northbridge/amd/pi/00730F01/iommu.c
index 1ff4cfb..5ff631c 100644
--- a/src/northbridge/amd/pi/00730F01/iommu.c
+++ b/src/northbridge/amd/pi/00730F01/iommu.c
@@ -16,7 +16,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <device/pci_ops.h>
 #include <lib.h>

static void iommu_read_resources(struct device *dev)
diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c
index c076c55..0040d8f 100644
--- a/src/northbridge/intel/gm45/bootblock.c
+++ b/src/northbridge/intel/gm45/bootblock.c
@@ -11,7 +11,6 @@
  * GNU General Public License for more details.
  */

-#include <device/pci_ops.h>

/* Just re-define these instead of including gm45.h. It blows up romcc. */
 #define D0F0_PCIEXBAR_LO 0x60
diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c
index 2c1bd58..7cd0eb4 100644
--- a/src/northbridge/intel/haswell/bootblock.c
+++ b/src/northbridge/intel/haswell/bootblock.c
@@ -11,7 +11,6 @@
  * GNU General Public License for more details.
  */

-#include <device/pci_ops.h>
 #include <cpu/intel/car/bootblock.h>
 #include "haswell.h"

diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index 604088b..8e74d80 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -11,7 +11,6 @@
  * GNU General Public License for more details.
  */

-#include <device/pci_ops.h>

/* Just re-define this instead of including i945.h. It blows up romcc. */
 #define PCIEXBAR	0x48
diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/nehalem/bootblock.c
index f96ff56..fa3f15b 100644
--- a/src/northbridge/intel/nehalem/bootblock.c
+++ b/src/northbridge/intel/nehalem/bootblock.c
@@ -11,7 +11,6 @@
  * GNU General Public License for more details.
  */

-#include <device/pci_ops.h>

static void bootblock_northbridge_init(void)
 {
diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c
index 97f6011..3389249 100644
--- a/src/northbridge/intel/nehalem/finalize.c
+++ b/src/northbridge/intel/nehalem/finalize.c
@@ -15,7 +15,6 @@
  */

#include <stdlib.h>
-#include <device/pci_ops.h>
 #include "nehalem.h"

#define PCI_DEV_SNB PCI_DEV(0, 0, 0)
diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c
index bd510b0..66fe40e 100644
--- a/src/northbridge/intel/pineview/bootblock.c
+++ b/src/northbridge/intel/pineview/bootblock.c
@@ -11,7 +11,6 @@
  * GNU General Public License for more details.
  */

-#include <device/pci_ops.h>
 #include <cpu/intel/car/bootblock.h>
 #include "pineview.h"

diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c
index 15e2de1..cdbe007 100644
--- a/src/northbridge/intel/sandybridge/bootblock.c
+++ b/src/northbridge/intel/sandybridge/bootblock.c
@@ -11,7 +11,6 @@
  * GNU General Public License for more details.
  */

-#include <device/pci_ops.h>

/* Just re-define this instead of including sandybridge.h. It blows up romcc. */
 #define PCIEXBAR	0x60
diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c
index 344cd80..618ee52 100644
--- a/src/northbridge/intel/sandybridge/pcie.c
+++ b/src/northbridge/intel/sandybridge/pcie.c
@@ -17,7 +17,6 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <device/pci_ops.h>
 #include <device/pciexp.h>
 #include <device/pci_ids.h>
 #include <assert.h>
diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c
index 1dfdf19..b1e384b 100644
--- a/src/northbridge/intel/x4x/bootblock.c
+++ b/src/northbridge/intel/x4x/bootblock.c
@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */

-#include <device/pci_ops.h>
 #include "iomap.h"
 #include "x4x.h"

diff --git a/src/northbridge/via/vx900/bootblock.c b/src/northbridge/via/vx900/bootblock.c
index 6679cdb..478893b 100644
--- a/src/northbridge/via/vx900/bootblock.c
+++ b/src/northbridge/via/vx900/bootblock.c
@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */

-#include <device/pci_ops.h>

#if CONFIG_ROM_SIZE == 0x80000
 #  define ROM_DECODE_MAP 0x00