Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37975 )
Change subject: mb/bap/ode_e20XX: Switch away from ROMCC_BOOTBLOCK ......................................................................
mb/bap/ode_e20XX: Switch away from ROMCC_BOOTBLOCK
Warning: not tested on hardware.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I34e84cd0efde37d2df2403928b8127c2f2947139 --- M src/mainboard/bap/ode_e20XX/Kconfig M src/mainboard/bap/ode_e20XX/Kconfig.name M src/mainboard/bap/ode_e20XX/Makefile.inc A src/mainboard/bap/ode_e20XX/bootblock.c D src/mainboard/bap/ode_e20XX/romstage.c 5 files changed, 31 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/37975/1
diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index 2a72deb..e59147f 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -21,7 +21,6 @@
config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/bap/ode_e20XX/Kconfig.name b/src/mainboard/bap/ode_e20XX/Kconfig.name index 54ddcac..a482846 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig.name +++ b/src/mainboard/bap/ode_e20XX/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_ODE_E20XX -# bool"ODE_e20xx" +config BOARD_ODE_E20XX + bool "ODE_e20xx" diff --git a/src/mainboard/bap/ode_e20XX/Makefile.inc b/src/mainboard/bap/ode_e20XX/Makefile.inc index 4d8eb8d..8747d2f 100644 --- a/src/mainboard/bap/ode_e20XX/Makefile.inc +++ b/src/mainboard/bap/ode_e20XX/Makefile.inc @@ -14,6 +14,8 @@ # GNU General Public License for more details. #
+bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/bap/ode_e20XX/bootblock.c b/src/mainboard/bap/ode_e20XX/bootblock.c new file mode 100644 index 0000000..8744547 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/bootblock.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f81866d/f81866d.h> + +#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) + +void bootblock_mainboard_early_init(void) +{ + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + pm_write8(0xea, 0x1); + + fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c deleted file mode 100644 index 505de38..0000000 --- a/src/mainboard/bap/ode_e20XX/romstage.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects - * (Written by Fabian Kunkel fabi@adv.bruhnspace.com for BAP) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pci_ops.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -#include <northbridge/amd/agesa/state_machine.h> -#include <superio/fintek/common/fintek.h> -#include <superio/fintek/f81866d/f81866d.h> - - -#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) - -void board_BeforeAgesa(struct sysinfo *cb) -{ - /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - outb(0xea, 0xcd6); - outb(0x1, 0xcd7); - - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); -}