[coreboot-gerrit] Change in coreboot[master]: Revert "broadwell: Switch to using common ACPI _SWS code"

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46734 )

Change subject: Revert "broadwell: Switch to using common ACPI _SWS code"
......................................................................

Revert "broadwell: Switch to using common ACPI _SWS code"

This reverts commit 81a4c85acf664156bb68807f681cd40928bf8267.

Reason for revert: Blocks merging Haswell and Broadwell together.

Tested on out-of-tree Acer Aspire E5-573, still boots.

Change-Id: I29c4ad9174ab84c7e9111daa0491ede9e1d639b4
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46734
Reviewed-by: Michael Niewöhner 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/acpi/platform.asl
M src/soc/intel/broadwell/ramstage.c
3 files changed, 64 insertions(+), 16 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 2430be6..6e57f0a 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -34,7 +34,6 @@
    select TSC_MONOTONIC_TIMER
    select SOC_INTEL_COMMON
    select INTEL_DESCRIPTOR_MODE_CAPABLE
-	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
    select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT
    select INTEL_GMA_ACPI
    select HAVE_POWER_STATE_AFTER_FAILURE
diff --git a/src/soc/intel/broadwell/acpi/platform.asl b/src/soc/intel/broadwell/acpi/platform.asl
index f404352..880b206 100644
--- a/src/soc/intel/broadwell/acpi/platform.asl
+++ b/src/soc/intel/broadwell/acpi/platform.asl
@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

-/* Enable ACPI _SWS methods */
-#include <soc/intel/common/acpi/acpi_wake_source.asl>
 #include <southbridge/intel/common/acpi/platform.asl>

/*
@@ -19,3 +17,21 @@
 {
    Return (Package (){ 0, 0 })
 }
+
+Scope (_SB)
+{
+	Method (_SWS)
+	{
+		/* Index into PM1 for device that caused wake */
+		Return (\PM1I)
+	}
+}
+
+Scope (_GPE)
+{
+	Method (_SWS)
+	{
+		/* Index into GPE for device that caused wake */
+		Return (\GPEI)
+	}
+}
diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c
index c414d62..57abf95 100644
--- a/src/soc/intel/broadwell/ramstage.c
+++ b/src/soc/intel/broadwell/ramstage.c
@@ -2,32 +2,63 @@

#include <acpi/acpi.h>
 #include <cbmem.h>
+#include <console/console.h>
 #include <device/device.h>
 #include <string.h>
 #include <soc/nvs.h>
 #include <soc/pm.h>
 #include <soc/ramstage.h>
 #include <soc/intel/broadwell/chip.h>
-#include <soc/intel/common/acpi.h>
-#include <assert.h>

-/* Save wake source information for calculating ACPI _SWS values */
-int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
+/* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */
+static void save_acpi_wake_source(struct global_nvs *gnvs)
 {
    struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
-	static uint32_t gpe0_sts[GPE0_REG_MAX];
-	int i;
+	uint16_t pm1;
+	int gpe_reg;

-	assert(ps != NULL);
+	if (!ps)
+		return;

-	*pm1 = ps->pm1_sts & ps->pm1_en;
+	pm1 = ps->pm1_sts & ps->pm1_en;

-	/* Mask off GPE0 status bits that are not enabled */
-	*gpe0 = &gpe0_sts[0];
-	for (i = 0; i < GPE0_REG_MAX; i++)
-		gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i];
+	/* Scan for first set bit in PM1 */
+	for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) {
+		if (pm1 & 1)
+			break;
+		pm1 >>= 1;
+	}

-	return GPE0_REG_MAX;
+	/* If unable to determine then return -1 */
+	if (gnvs->pm1i >= 16)
+		gnvs->pm1i = -1;
+
+	/* Scan for first set bit in GPE registers */
+	gnvs->gpei = -1;
+	for (gpe_reg = 0; gpe_reg < GPE0_REG_MAX; gpe_reg++) {
+		u32 gpe = ps->gpe0_sts[gpe_reg] & ps->gpe0_en[gpe_reg];
+		int start = gpe_reg * GPE0_REG_SIZE;
+		int end = start + GPE0_REG_SIZE;
+
+		if (gpe == 0) {
+			if (!gnvs->gpei)
+				gnvs->gpei = end;
+			continue;
+		}
+
+		for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) {
+			if (gpe & 1)
+				break;
+			gpe >>= 1;
+		}
+	}
+
+	/* If unable to determine then return -1 */
+	if (gnvs->gpei >= (GPE0_REG_MAX * GPE0_REG_SIZE))
+		gnvs->gpei = -1;
+
+	printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n",
+	       gnvs->pm1i, gnvs->gpei);
 }

static void s3_resume_prepare(void)
@@ -40,6 +71,8 @@

if (!acpi_is_wakeup_s3())
    	memset(gnvs, 0, sizeof(struct global_nvs));
+	else
+		save_acpi_wake_source(gnvs);
 }

void broadwell_init_pre_device(void *chip_info)