[coreboot-gerrit] Change in coreboot[master]: src/soc/tigerlake: Add memory configuration support for Jasper Lake

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39135 )

Change subject: src/soc/tigerlake: Add memory configuration support for Jasper Lake
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Patch Set 21:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39135/7/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/jsl_memcfg_init.h:

https://review.coreboot.org/c/coreboot/+/39135/7/src/soc/intel/tigerlake/inc... 
PS7, Line 103: uint16_t rcomp_resistor[3];
> Sure, Furquan. We would raise a crosbug and share the relevant document.

I have asked for the relevant info for the DQ-DQs mapping in this crosbug - b/150154457 - c#8. You can use that bug.

As for the Rcomp resistor values, it matches with the resistors being populated in the schematics.