Attention is currently required from: Shelley Chen, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59193 )
Change subject: WIP libpayload: Parse DDR Information through coreboot tables WIP ......................................................................
Patch Set 2:
(4 comments)
File payloads/libpayload/libc/coreboot.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133280): https://review.coreboot.org/c/coreboot/+/59193/comment/ff44e7fd_d4393b75 PS2, Line 357: cb_parse_mem_chip_info(ptr, info); code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133280): https://review.coreboot.org/c/coreboot/+/59193/comment/8104485c_6152b84d PS2, Line 357: cb_parse_mem_chip_info(ptr, info); please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133280): https://review.coreboot.org/c/coreboot/+/59193/comment/c33b4781_92700611 PS2, Line 358: break; code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133280): https://review.coreboot.org/c/coreboot/+/59193/comment/25060187_1b0b385c PS2, Line 358: break; please, no spaces at the start of a line