Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55756 )
Change subject: [Don't Merge] Performs disable for Serial Io UART0 Controller ......................................................................
[Don't Merge] Performs disable for Serial Io UART0 Controller
TEST=lspci 00:1e.0 shows Offset 0x84, Bit[1:0] set to 1 and Offset 0xA0, Bit[19:16] set to 1. Meaning, UART0 will power gate whe idle.
Change-Id: Ie3f7fb426b3e0f76873a1e6f7e2263571fd79b0f Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/alderlake/smihandler.c M src/soc/intel/common/block/cse/disable_heci.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 61 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/55756/1
diff --git a/src/soc/intel/alderlake/smihandler.c b/src/soc/intel/alderlake/smihandler.c index 5b53038..eb04400 100644 --- a/src/soc/intel/alderlake/smihandler.c +++ b/src/soc/intel/alderlake/smihandler.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <console/console.h> #include <device/pci_def.h> #include <intelblocks/cse.h> #include <intelblocks/smihandler.h> @@ -19,9 +20,10 @@ const struct soc_intel_alderlake_config *config;
config = config_of_soc(); - - if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) + printk(BIOS_ERR, "UART 0 is calling \n"); +// if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) heci_disable(); + uart_disable(); }
int smihandler_soc_disable_busmaster(pci_devfn_t dev) diff --git a/src/soc/intel/common/block/cse/disable_heci.c b/src/soc/intel/common/block/cse/disable_heci.c index 664a2f7..479b755 100644 --- a/src/soc/intel/common/block/cse/disable_heci.c +++ b/src/soc/intel/common/block/cse/disable_heci.c @@ -15,6 +15,10 @@ #define CSME0_BAR 0x0 #define CSME0_FID 0xb0
+#define UART0_FBE 0xf +#define UART0_BAR 0x0 +#define UART0_FID 0xf0 + /* Disable HECI using Sideband interface communication */ void heci_disable(void) { @@ -46,3 +50,55 @@ /* hide p2sb device */ p2sb_hide(); } + +/* Disable uart using Sideband interface communication */ +void uart_disable(void) +{ + struct pcr_sbi_msg msg = { + .pid = PID_SERIALIO, + .offset = 0xA0, + .opcode = PCR_WRITE, + .is_posted = false, + .fast_byte_enable = UART0_FBE, + .bar = UART0_BAR, + .fid = UART0_FID + }; + struct pcr_sbi_msg msg1 = { + .pid = PID_SERIALIO, + .offset = 0x84, + .opcode = PCR_WRITE, + .is_posted = false, + .fast_byte_enable = UART0_FBE, + .bar = UART0_BAR, + .fid = UART0_FID + }; + + /* Bit 16-18: Set to make UART0 Function disable */ + uint32_t data32 = 0x70000; + uint8_t response; + int status; + + /* unhide p2sb device */ + p2sb_unhide(); + + printk(BIOS_ERR, "Subrata\n"); + /* Send SBI command to make HECI#1 function disable */ + status = pcr_execute_sideband_msg(&msg, &data32, &response); + if (status || response) + printk(BIOS_ERR, "Fail to make UART0 function 0xA0 disable\n"); + + data32 = 0x3; + response = 0; + + /* Send SBI command to make HECI#1 function disable */ + status = pcr_execute_sideband_msg(&msg1, &data32, &response); + if (status || response) + printk(BIOS_ERR, "Fail to make UART0 function 0x84 disable\n"); + + /* Ensure to Lock SBI interface after this command */ + p2sb_disable_sideband_access(); + + /* hide p2sb device */ + p2sb_hide(); +} + diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index f52cc89..5604854 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -153,6 +153,7 @@ int heci_reset(void); /* Disable HECI using Sideband interface communication */ void heci_disable(void); +void uart_disable(void);
/* Reads config value from a specified offset in the CSE PCI Config space. */ uint32_t me_read_config32(int offset);