[coreboot-gerrit] [M] Change in coreboot[master]: drivers/intel/gma: Hook up libgfxinit in romstage

[Jérémy Compostella (Code Review)]

Attention is currently required from: Bora Guvendik, Zhixing Ma, Anil Kumar K, Hannah Williams, Cliff Huang, Nico Huber, Michał Żygowski, Subrata Banik, Paul Menzel, Arthur Heymans.

Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70276 )

Change subject: drivers/intel/gma: Hook up libgfxinit in romstage
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Patch Set 15:

(1 comment)

File src/drivers/intel/gma/Kconfig:

https://review.coreboot.org/c/coreboot/+/70276/comment/ca3cb420_a2bfff9a 
PS13, Line 103: Graphic MMIO address
> Are you saying, to allocate any memory range to GFX BAR0? BAR0 is PCI offset 0x10 which is `GTTMMADR`.

I am confused. To my understanding GFX MMIO programmed we configure in PCI BAR 0 has nothing to do with the Global Translation Table which is hosted in DRAM.