[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning

[Bao Zheng (Code Review)]

Attention is currently required from: Jason Glenesk, Nico Huber, Raul Rangel, Marshall Dawson, Paul Menzel, Zheng Bao, Felix Held.
Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59918 )

Change subject: soc/amd/cezanne: FSP: Add UPD entry for eDP tuning
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Patch Set 7:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/59918/comment/d078e585_eb850b2d 
PS5, Line 11: https://partnerissuetracker.corp.google.com/issues/203061533#comment6
> Ok, so the issue is private. Is the information too? Generally, it's […]

Done.
The document is just for AMD internal debugging.

https://review.coreboot.org/c/coreboot/+/59918/comment/4463081e_3a32fc60 
PS5, Line 11: https://partnerissuetracker.corp.google.com/issues/203061533#comment6
> In this case, I was wondering about the FSP. […]

Done.
Add some information in commit log.

Patchset:

PS5:
> Sorry, eDP is part of graphics initialization, which is currently not FLOSS on AMD hardware. […]

Done