Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35026 )
Change subject: soc/intel/{cnl, icl}: Cache the TSEG region ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
Patch Set 2:
'cbmem -t' from this commit please.
sorry, just to understand your question.
- do you want to capture the cbmem -t time with this commit as i thought i have captured CB:34995 commit msg already while exposing the new API.
This commit 36b7091 exactly. And put the commit hash together with the data in the comments this time. The patchtrain evolved so heavily that CB: references are obscure.
or
- You wish to get cbmem -t numbers with this CL. Its already shared here right ?
CB:34791
With POSTCAR_STAGE=y and (CB:34805 + 34995) [romstage -> postcar -> ramstage]
Total Time till picking kernel: 813,549 Total Time till picking payload: 635,250
You posted the following under CB:34791.
Aug 20 09:55 Total Time: 813,549
AFAICS this result was from a boot with CB:34995 patchset #1 and CB:34791 patchset #11. While it did set TSEG as WB for the postcar_frame, it also immediately called set_var_mtrr() to program CBMEM region as WRPROT. At the time of that run, it is questionable if cbmem_top() was properly aligned to make that set_var_mtrr() call.
In short, I want result from a boot that definetly does not call set_var_mtrr() at all, has POSTCAR_STAGE=y, and definetly adds TSEG as WB in the postcar frame. Commit 36b7091 does that.
Let me compare the delta between data posted above with POSTCAR_STAGE=y and (CB:34805 + 34995) [romstage -> postcar -> ramstage] vs POSTCAR_STAGE=y + CB:34995 + CB: 35026
#1 With POSTCAR_STAGE=y and (CB:34805 + 34995) [romstage -> postcar -> ramstage]
Aug 20 09:55
Total Time: 813,549
Total Time till picking kernel: 813,549 Total Time till picking payload: 635,250
#2 With POSTCAR_STAGE=y and (CB:34995 + CB: 35026) [romstage -> postcar -> ramstage]
Aug 23
Total Time: 818,078
Total Time till picking kernel: 818,078 Total Time till picking payload: 639,809
so #1 vs #2 delta is ~4ms