Attention is currently required from: Sean Rhodes.
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70050 )
Change subject: soc/intel: Adopt new common/pmbase ......................................................................
soc/intel: Adopt new common/pmbase
Change-Id: I473ebefcf8e0c929f6cbf6b5c0d7e8f5af72856d Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/acer/aspire_vn7_572g/mainboard.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smitraphandler.c M src/soc/intel/skylake/pmc.c 6 files changed, 39 insertions(+), 51 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/70050/1
diff --git a/src/mainboard/acer/aspire_vn7_572g/mainboard.c b/src/mainboard/acer/aspire_vn7_572g/mainboard.c index eba9e98..171b193 100644 --- a/src/mainboard/acer/aspire_vn7_572g/mainboard.c +++ b/src/mainboard/acer/aspire_vn7_572g/mainboard.c @@ -126,9 +126,10 @@ /* Clear below events and go back to sleep */ /* Clear ABase PM1_STS - RW/1C set bits */ pmc_clear_pm1_status(); + /* Clear ABase GPE0_STS[127:96] - RW/1C set bits */ - uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); - outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); + pm_rwc32(GPE0_STS(GPE_STD)); + /* Clear xHCI PM_CS[PME_Status] - RW/1C - and disable xHCI PM_CS[PME_En] */ pci_update_config16(PCH_DEV_XHCI, 0x74, ~0x100, 0x8000); diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 765b2c8..1f641de 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -79,7 +79,7 @@ uint32_t soc_get_smi_status(uint32_t generic_sts) { if (generic_sts == 0 && !(pmc_read_pm1_control() & SCI_EN)) { - uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + uint16_t pm1_sts = pm_read16(PM1_STS);
/* Fake PM1 status bit if power button pressed. */ if (pm1_sts & PWRBTN_STS) diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index ea365d0..87056c5 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -124,10 +124,7 @@
static uint32_t pmc_reset_smi_status(void) { - uint32_t smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS); - outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS); - - return soc_get_smi_status(smi_sts); + return soc_get_smi_status(pm_rwc32(SMI_STS)); }
static uint32_t print_smi_status(uint32_t smi_sts) @@ -162,7 +159,7 @@ /* Read events set in PM1_EN register. */ uint16_t pmc_read_pm1_enable(void) { - return inw(ACPI_BASE_ADDRESS + PM1_EN); + return pm_read16(PM1_EN); }
uint32_t pmc_clear_smi_status(void) @@ -174,58 +171,48 @@
uint32_t pmc_get_smi_en(void) { - return inl(ACPI_BASE_ADDRESS + SMI_EN); + return pm_read32(SMI_EN); }
void pmc_enable_smi(uint32_t mask) { - uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); - smi_en |= mask; - outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); + pm_setbits32(SMI_EN, mask); }
void pmc_disable_smi(uint32_t mask) { - uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); - smi_en &= ~mask; - outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); + pm_clrbits32(SMI_EN, mask); }
/* PM1 */ void pmc_enable_pm1(uint16_t events) { - outw(events, ACPI_BASE_ADDRESS + PM1_EN); + pm_write16(PM1_EN, events); }
uint32_t pmc_read_pm1_control(void) { - return inl(ACPI_BASE_ADDRESS + PM1_CNT); + return pm_read32(PM1_CNT); }
void pmc_write_pm1_control(uint32_t pm1_cnt) { - outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); + pm_write32(PM1_CNT, pm1_cnt); }
void pmc_enable_pm1_control(uint32_t mask) { - uint32_t pm1_cnt = pmc_read_pm1_control(); - pm1_cnt |= mask; - pmc_write_pm1_control(pm1_cnt); + pm_setbits32(PM1_CNT, mask); }
void pmc_disable_pm1_control(uint32_t mask) { - uint32_t pm1_cnt = pmc_read_pm1_control(); - pm1_cnt &= ~mask; - pmc_write_pm1_control(pm1_cnt); + pm_clrbits32(PM1_CNT, mask); }
static uint16_t reset_pm1_status(void) { - uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS); - return pm1_sts; + return pm_rwc16(PM1_STS); }
static uint16_t print_pm1_status(uint16_t pm1_sts) @@ -284,16 +271,12 @@ /* GPE */ static void pmc_enable_gpe(int gpe, uint32_t mask) { - uint32_t gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(gpe)); - gpe0_en |= mask; - outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(gpe)); + pm_setbits32(GPE0_EN(gpe), mask); }
static void pmc_disable_gpe(int gpe, uint32_t mask) { - uint32_t gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(gpe)); - gpe0_en &= ~mask; - outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(gpe)); + pm_clrbits32(GPE0_EN(gpe), mask); }
void pmc_enable_std_gpe(uint32_t mask) @@ -322,16 +305,13 @@ /* This is reserved GPE block and specific to chipset */ if (i == GPE_STD) continue; - uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); - outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(i)); + pm_rwc32(GPE0_STS(i)); } }
static uint32_t reset_std_gpe_status(void) { - uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); - outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); - return gpe_sts; + return pm_rwc32(GPE0_STS(GPE_STD)); }
static uint32_t print_std_gpe_sts(uint32_t gpe_sts) @@ -423,16 +403,16 @@
memset(ps, 0, sizeof(*ps));
- ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); + ps->pm1_sts = pm_read16(PM1_STS); + ps->pm1_en = pm_read16(PM1_EN); ps->pm1_cnt = pmc_read_pm1_control();
printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", ps->pm1_sts, ps->pm1_en, ps->pm1_cnt);
for (i = 0; i < GPE0_REG_MAX; i++) { - ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); - ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i)); + ps->gpe0_sts[i] = pm_read32(GPE0_STS(i)); + ps->gpe0_en[i] = pm_read32(GPE0_EN(i)); printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", i, ps->gpe0_sts[i], i, ps->gpe0_en[i]); } @@ -480,7 +460,7 @@ return acpi_get_sleep_type() == ACPI_S3;
/* Read power state from PMC ABASE */ - if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) + if (!(pm_read16(PM1_STS) & WAK_STS)) return 0;
return acpi_sleep_from_pm1(pmc_read_pm1_control()) == ACPI_S3; @@ -506,9 +486,9 @@ if (stopwatch_expired(&sw)) return rc;
- sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank)); + sts = pm_read32(GPE0_STS(bank)); if (sts & mask) { - outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank)); + pm_write32(GPE0_STS(bank), mask); rc = 1; } } while (sts & mask); diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 0a277f0..f5e3e37 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -156,7 +156,7 @@ /* First, disable further SMIs */ pmc_disable_smi(SLP_SMI_EN); /* Figure out SLP_TYP */ - reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); + reg32 = pm_read32(PM1_CNT); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = acpi_sleep_from_pm1(reg32);
diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c index 99825f1..2d26f94 100644 --- a/src/soc/intel/common/block/smm/smitraphandler.c +++ b/src/soc/intel/common/block/smm/smitraphandler.c @@ -43,7 +43,7 @@ void smihandler_southbridge_mc( const struct smm_save_state_ops *save_state_ops) { - u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); + u32 reg32 = pm_read32(SMI_EN);
/* Are microcontroller SMIs enabled? */ if ((reg32 & MCSMI_EN) == 0) diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index 61662d2..bf2357c 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -84,10 +84,7 @@ S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS | DIS_SLP_X_STRCH_SUS_UP);
/* Enable SCI and clear SLP requests. */ - reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); - reg32 &= ~SLP_TYP; - reg32 |= SCI_EN; - outl(reg32, ACPI_BASE_ADDRESS + PM1_CNT); + pm_clrsetbits32(PM1_CNT, SLP_TYP, SCI_EN);
pmc_set_acpi_mode();