Damien Zammit (damien@zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17645
-gerrit
commit 8684bf8685a58fcc13792d1d6cf3a6c706677d14 Author: Damien Zammit damien@zamaudio.com Date: Wed Nov 30 14:32:20 2016 +1100
nb/intel/gm45: Clear GTT correctly for IOMMU (igd)
Bit 11 of BDF(0,0,0), GGC(0x52) is actually the correct bit for detecting VT mode on IGD, not bit 10, according to GM45 Intel chipset datasheet.
Now we use the correct bit for detecting VT mode on IGD.
UNTESTED ON HW.
Change-Id: I60268072619253443a04e61c9617f2260d5a750c Signed-off-by: Damien Zammit damien@zamaudio.com --- src/northbridge/intel/gm45/iommu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 77aba94..76432fb 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -46,8 +46,8 @@ void init_iommu() MCHBAR32(0x20) = IOMMU_BASE4 | 1; /* all other DMA sources */
/* clear GTT */ - u32 gtt = pci_read_config16(PCI_DEV(0, 0, 0), 0x52); - if (gtt & 0x400) { /* VT mode */ + u16 ggc = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_GGC); + if (ggc & 0x800) { /* VT mode */ pci_devfn_t igd = PCI_DEV(0, 2, 0);
/* setup somewhere */