[coreboot-gerrit] [M] Change in coreboot[master]: soc/intel/cmn/cse: Create API to perform essential post EOP operations

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69977 )

Change subject: soc/intel/cmn/cse: Create API to perform essential post EOP operations
......................................................................

soc/intel/cmn/cse: Create API to perform essential post EOP operations

This patch creates an API that can perform essential CSE operation
after sending the EOP command to the CSE and before booting to OS.

Lists of operation are
- Perform global reset lock
- Put HECI1 to D0i3 and disable the HECI1 if the user selects
- Set D0I3 for all HECI devices.

Additionally, ensures that CSE .final operation is not sending EOP
and other essential operations if the SoC user selects
SOC_INTEL_CSE_SEND_EOP_LATE config.

BUG=none
TEST=Able to boot Google/Rex after sending CSE EOP late.

Signed-off-by: Subrata Banik 
Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 54 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/69977/1

diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index fdeb01e..6434371 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -1256,11 +1256,34 @@
 }

/*
+ * This function to perform essential post EOP cse related operations
+ * upon SoC selecting `SOC_INTEL_CSE_SEND_EOP_LATE` config
+ */
+void cse_late_finalize(void)
+{
+	if (!CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE))
+		return;
+
+	if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT))
+		cse_final_ready_to_boot();
+
+	if (!CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
+		cse_final_end_of_firmware();
+}
+
+/*
  * `cse_final` function is native implementation of equivalent events performed by
  * each FSP NotifyPhase() API invocations.
  */
 static void cse_final(struct device *dev)
 {
+	/*
+	 * SoC user decided to send EOP late hence, the `cse_late_finalize()` will
+	 * take care of essential post EOP cse related operations.
+	 */
+	if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE))
+		return;
+
    /* 1. Send EOP to CSE if not done.*/
    if (CONFIG(SOC_INTEL_CSE_SET_EOP))
    	cse_send_end_of_post();
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index f7aae1c..564ff48 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -542,6 +542,12 @@
 void cse_send_end_of_post(void);

/*
+ * This function to perform essential post EOP cse related operations
+ * upon SoC selecting `SOC_INTEL_CSE_SEND_EOP_LATE` config
+ */
+void cse_late_finalize(void);
+
+/*
  * SoC override API to make heci1 disable using PCR.
  *
  * Allow SoC to implement heci1 disable override due to PSF registers being