Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Tim Wawrzynczak, Christian Walter, Jes Klinke, Subrata Banik, Julius Werner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44359
to look at the new patch set (#17).
Change subject: mainboard/google/volteer: Disable S0i3.4 if cr50 firmware is too old ......................................................................
mainboard/google/volteer: Disable S0i3.4 if cr50 firmware is too old
For Volteer (and future Tiger Lake boards) we can enable mode S0i3.4 only if we know that the Cr50 is generating 100us interrupt pulses. We have to do so, because the SoC is not guaranteed to detect pulses shorter than 100us in S0i3.4 substate.
A new Kconfig setting CR50_USE_LONG_INTERRUPT_PULSES controls new code running in verstage, which will program a new Cr50 register, provided that Cr50 firmware is new enough to support the register.
This CL adds code to detect the case when Cr50 is unable to generate longer pulses, and in that case disable the S0i3.4 substate. This will increase power usage slightly, but guarantee that the GPIO block in the SoC does not switch to a slower sampling clock. In practice, this case will only be encountered in the factory, before the Cr50 chip is updated to a new RW image.
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x BUG=b:154333137
Change-Id: Idef1fffd410a345678da4b3c8aea46ac74a01470 Signed-off-by: Jes Bodi Klinke jbk@chromium.org --- M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/soc/intel/tigerlake/chip.h 3 files changed, 23 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/44359/17