[coreboot-gerrit] [S] Change in coreboot[master]: soc/rockchip/rk3288/clock.c: Remove trailing semicolon

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67965 )

Change subject: soc/rockchip/rk3288/clock.c: Remove trailing semicolon
......................................................................

soc/rockchip/rk3288/clock.c: Remove trailing semicolon

Signed-off-by: Elyes Haouas 
Change-Id: I0d03bd43b33570ee50f145ea6fd716c4072a11d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67965
Tested-by: build bot (Jenkins) 
Reviewed-by: Julius Werner 
---
M src/soc/rockchip/rk3288/clock.c
1 file changed, 14 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Julius Werner: Looks good to me, approved

diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index 1576a6a..c2f93f5 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -53,7 +53,7 @@
    .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
    _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
    	       (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
-		       "divisors on line " STRINGIFY(__LINE__));
+		       "divisors on line " STRINGIFY(__LINE__))

/* Keep divisors as low as possible to reduce jitter and power usage. */
 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);