Aaron Durbin (adurbin@chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13792
-gerrit
commit 94595ced304cc18453b098d81b0c20ef530f4c45 Author: Aaron Durbin adurbin@chromium.org Date: Wed Feb 24 19:00:03 2016 -0600
soc/intel/apollolake: provide function to setup uart pads and controller
Instead of pushing the same code into each mainboard for configuring the the UART pads and initializing the host contoller provide a function to perform all the actions on behalf of the mainboard. The set of pads configured is dictated by the CONFIG_UART_FOR_CONSOLE Kconfig option.
Change-Id: I06c499c7ee056b970468e0386d4bb1bc26537247 Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/soc/intel/apollolake/include/soc/uart.h | 3 +++ src/soc/intel/apollolake/uart_early.c | 32 ++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h index fd535fb..16f09b1 100644 --- a/src/soc/intel/apollolake/include/soc/uart.h +++ b/src/soc/intel/apollolake/include/soc/uart.h @@ -25,4 +25,7 @@
void lpss_console_uart_init(void);
+/* Initialize the console UART including the pads for the configured UART. */ +void soc_console_uart_init(void); + #endif /* _SOC_APOLLOLAKE_UART_H_ */ diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c index d3b1d80..4ee4a38 100644 --- a/src/soc/intel/apollolake/uart_early.c +++ b/src/soc/intel/apollolake/uart_early.c @@ -22,12 +22,21 @@ static void lpss_uart_write(uint16_t reg, uint32_t val) write32((void *)base, val); }
+static inline int invalid_uart_for_console(void) +{ + /* There are actually only 2 UARTS, and they are named UART1 and + * UART2. They live at pci functions 1 and 2 respectively. */ + if (CONFIG_UART_FOR_CONSOLE > 2 || CONFIG_UART_FOR_CONSOLE < 1) + return 1; + return 0; +} + void lpss_console_uart_init(void) { uint32_t clk_sel; device_t uart = _LPSS_PCI_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
- if (CONFIG_UART_FOR_CONSOLE > 2) + if (invalid_uart_for_console()) return;
/* Enable BAR0 for the UART -- this is where the 8250 registers hide */ @@ -59,3 +68,24 @@ unsigned int uart_platform_refclk(void) /* That's within 0.5% of the actual value we've set earlier */ return 115200 * 16; } + +static const struct pad_config uart_gpios[] = { + PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */ + PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */ + PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */ +}; + +void soc_console_uart_init(void) +{ + /* Get a 0-based pad index. See invalid_uart_for_console() above. */ + const int pad_index = CONFIG_UART_FOR_CONSOLE - 1; + + if (invalid_uart_for_console()) + return; + + /* Configure the 2 pads per UART. */ + gpio_configure_pads(&uart_gpios[pad_index * 2], 2); + + lpss_console_uart_init(); +}